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db14-000202-01 LSIFC929X dual channel fibre channel i/o processor technical manual june 2003 version 2.0
ii copyright 2002, 2003 by lsi logic corporation. all rights reserved. this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?er of lsi logic corporation. lsi logic products are not intended for use in life-support appliances, devices, or systems. use of any lsi logic product in such applications without written consent of the appropriate lsi logic of?er is prohibited. db14-000202-01, june 2003 this document describes the lsi logic corporation LSIFC929X dual channel fibre channel i/o processor and will remain the of?ial reference source for all revisions/releases of this product until rescinded by an update. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright 2002, 2003 by lsi logic corporation. all rights reserved. trademark acknowledgment lsi logic, the lsi logic logo design, fusion-mpt, and gigablaze are trademarks or registered trademarks of lsi logic corporation. arm is a registered trademark of arm ltd., used under license. all other brand and product names may be trademarks of their respective companies. db to receive product literature, visit us at http://www.lsilogic.com. for a current list of our distributors, sales of?es, and design resource centers, view our web page located at http://www.lsilogic.com/contacts/index.html
LSIFC929X dual channel fibre channel i/o processor technical manual iii copyright 2002, 2003 by lsi logic corporation. all rights reserved. preface this book is the primary reference and technical manual for the LSIFC929X dual channel fibre channel i/o processor. it contains a complete functional description for the LSIFC929X and includes complete physical and electrical speci?ations for the product. audience this document was prepared for logic designers and applications engineers and is intended to provide an overview of the lsi logic LSIFC929X and to explain how to use the LSIFC929X in the initial stages of system design. this document assumes that you have some familiarity with microprocessors and related support devices. the people who bene? from this book are ? engineers and managers who are evaluating the LSIFC929X for possible use in a system ? engineers who are designing the LSIFC929X into a system organization this document has the following chapters and appendixes: ? chapter 1, introduction , provides a general description of the LSIFC929X. ? chapter 2, fibre channel overview , brie? describes some key elements of fibre channel, including layers, topologies, and classes of service.
iv preface copyright 2002, 2003 by lsi logic corporation. all rights reserved. ? chapter 3, LSIFC929X overview , provides an introduction to the basic features of the LSIFC929X, including the message interface, protocol assist engines, and support components. ? chapter 4, signal descriptions , lists and describes the signals on the LSIFC929X. ? chapter 5, pci-x functional description , describes the pci-x features contained in the LSIFC929X. ? chapter 6, registers , brie? describes the pci-x address space, the con?uration registers, and the host interface registers. ? chapter 7, speci?ations , describes the electrical speci?ations of the LSIFC929X, and provides pinout information and packaging dimensions. ? appendix a, register summary , is a register summary. ? appendix b, reference speci?ations , lists several speci?ations and applicable world wide web urls that may bene? the reader. ? appendix c, glossary of terms and abbreviations , provides de?itions for terms and abbreviations used in this manual. related publications fusion-mpt message passing interface speci?ation , volume 1.2, document no. db14-000174-02 pci local bus speci?ation, version 2.2 pci-x addendum to the pci local bus speci?ation, version 1.0a conventions used in this manual the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. signals that are active low end in a ?. hexadecimal numbers are indicated by the pre? ?x ?or example, 0x32cf. binary numbers are indicated by the pre? ?b ?or example, 0b0011.0010.1100.1111.
preface v copyright 2002, 2003 by lsi logic corporation. all rights reserved. revision record revision date remarks 0.5 3/2002 first advance information release. 2.0 6/2003 final release.
vi preface copyright 2002, 2003 by lsi logic corporation. all rights reserved.
LSIFC929X dual channel fibre channel i/o processor technical manual vii copyright 2002, 2003 by lsi logic corporation. all rights reserved. contents chapter 1 introduction 1.1 overview 1-1 1.1.1 hardware features 1-1 1.1.2 fc features 1-2 1.1.3 software features 1-3 1.1.4 os support 1-3 1.1.5 targeted applications 1-3 1.2 general description 1-4 1.2.1 multifunction pci-x 1-5 1.2.2 autospeed negotiation 1-5 1.2.3 autotopology negotiation 1-5 1.2.4 failover and load balancing 1-6 1.3 hardware overview 1-6 1.3.1 pci/pci-x interface 1-7 1.3.2 32-bit memory controller 1-7 1.3.3 i/o processor 1-7 1.3.4 system interface 1-8 1.3.5 integrated 2 gbit/s transceivers 1-8 1.3.6 link controllers 1-8 1.3.7 datapath 1-8 1.3.8 context managers 1-8 1.4 initiator operations 1-9 1.5 target operations 1-9 1.6 diagnostics 1-9 chapter 2 fibre channel overview 2.1 introduction 2-2 2.2 fc layers 2-3 2.3 frames 2-4
viii contents copyright 2002, 2003 by lsi logic corporation. all rights reserved. 2.4 exchanges 2-5 2.5 fc ports 2-7 2.6 fc topologies 2-7 2.6.1 point-to-point topology 2-8 2.6.2 fabric topology 2-8 2.6.3 arbitrated loop topology 2-8 2.7 classes of service 2-9 chapter 3 LSIFC929X overview 3.1 introduction 3-1 3.2 message interface 3-3 3.2.1 messages 3-3 3.2.2 message flow 3-4 3.3 scsi message 3-6 3.4 lan message 3-6 3.5 target message 3-8 3.6 support components 3-8 3.6.1 ssram memory 3-9 3.6.2 flash rom 3-10 3.6.3 serial eeprom 3-10 chapter 4 signal descriptions 4.1 pci/pci-x interface 4-3 4.2 fibre channel interface 4-7 4.3 memory interface 4-10 4.4 con?uration and miscellaneous 4-14 4.5 test and i/o processor debug 4-15 4.6 power and ground 4-16 chapter 5 pci-x functional description 5.1 overview 5-1 5.2 pci-x addressing 5-2 5.2.1 pci con?uration space 5-2 5.2.2 pci i/o space 5-3 5.2.3 pci memory space 5-3 5.3 pci/pci-x bus commands and implementation 5-3
contents ix copyright 2002, 2003 by lsi logic corporation. all rights reserved. 5.3.1 interrupt acknowledge command 5-5 5.3.2 special cycle command 5-5 5.3.3 i/o read command 5-5 5.3.4 i/o write command 5-5 5.3.5 memory read command 5-5 5.3.6 memory read dword command 5-5 5.3.7 memory write command 5-6 5.3.8 alias to memory read block command 5-6 5.3.9 alias to memory write block command 5-6 5.3.10 con?uration read command 5-6 5.3.11 con?uration write command 5-6 5.3.12 memory read multiple command 5-7 5.3.13 split completion command 5-7 5.3.14 dual address cycles (dac) command 5-8 5.3.15 memory read line command 5-8 5.3.16 memory read block command 5-8 5.3.17 memory write and invalidate command 5-8 5.3.18 memory write block command 5-9 5.4 pci arbitration 5-9 5.5 pci cache mode 5-9 chapter 6 registers 6.1 pci-x con?uration space register description 6-2 6.2 pci i/o space and memory space register description 6-32 6.3 shared memory 6-44 chapter 7 speci?ations 7.1 electrical requirements 7-2 7.2 ac timing 7-7 7.2.1 pci/pci-x interface timings 7-7 7.2.2 fibre channel interface timings 7-7 7.2.3 memory interface timings 7-8 7.3 packaging 7-11 7.4 mechanical drawing 7-18 7.5 package thermal considerations 7-19
x contents copyright 2002, 2003 by lsi logic corporation. all rights reserved. appendix a register summary appendix b reference speci?ations appendix c glossary of terms and abbreviations index customer feedback
contents xi copyright 2002, 2003 by lsi logic corporation. all rights reserved. figures 1.1 LSIFC929X typical implementation 1-5 1.2 LSIFC929X functional block diagram 1-7 2.1 fc layers 2-2 2.2 link control frame 2-4 2.3 data frame 2-4 2.4 exchange to character 2-5 2.5 fcp exchange 2-6 2.6 write event trellis 2-7 2.7 point-to-point topology 2-8 2.8 fabric topology 2-8 2.9 arbitrated loop topology 2-9 3.1 LSIFC929X block diagram 3-2 3.2 LSIFC929X message flow 3-5 3.3 lan protocol stack 3-7 3.4 LSIFC929X typical implementation 3-9 4.1 LSIFC929X functional signal grouping 4-2 7.1 ssram read/write/read timing waveforms 7-8 7.2 flash rom read timing waveforms 7-9 7.3 flash rom write timing waveforms 7-10 7.4 LSIFC929X 456-pin pbga top view 7-12 7.5 456-pad plastic ball grid array 7-18
xii contents copyright 2002, 2003 by lsi logic corporation. all rights reserved.
contents xiii copyright 2002, 2003 by lsi logic corporation. all rights reserved. tables 4.1 pci/pci-x interface 4-3 4.2 fibre channel interface 4-7 4.3 memory interface 4-10 4.4 con?uration and miscellaneous 4-14 4.5 test and i/o processor debug 4-15 4.6 power and ground 4-16 5.1 pci/pci-x bus commands and encodings 5-4 6.1 LSIFC929X pci-x con?uration space address map 6-3 6.2 device id values 6-5 6.3 multiple message enable field bit encoding 6-25 6.4 maximum outstanding split transactions 6-29 6.5 maximum memory read byte count 6-29 6.6 pci i/o space address map 6-33 6.7 pci memory [0] address map 6-33 6.8 pci memory [1] address map 6-34 6.9 interrupt signal routing 6-41 7.1 absolute maximum stress ratings 7-3 7.2 operating conditions 7-3 7.3 capacitance 7-4 7.4 input signals (fault1/, fault0/, mode[7:0], switch, hotswapen/) 7-4 7.5 schmitt input signals (refclk, tck, tdi, trst/, tms_chip, tms_ice) 7-4 7.6 4 ma bidirectional signals (lipreset/, odis1, odis0, bypass1/, bypass0/, md[31:0], ma[21:0], mwe[1:0]/, flashcs/, bwe[3:0]/, ramcs/, zz, mp[3:0], scl, sda, rxlos1, rxlos0, adsc/, adv/, tdo) 7-4 7.7 8 ma bidirectional signals (moddef1[2:0], moddef0[2:0], gpio[5:0], moe[1:0]/, led[4:0]/, mclk) 7-5 7.8 pci input signals (pciclk, gnt/, idsel, rst/) 7-5 7.9 pci bidirectional signals (ad[63:0], c_be[7:0]/, frame/, irdy/, trdy/, stop/, perr/, par, ack64/, enum/, 64en/) 7-6 7.10 pci output signals (par64, req/, req64/, devsel/, serr/, inta/, intb/) 7-6 7.11 ssram read/write/read timings 7-8 7.12 flash rom read timings 7-9
xiv contents copyright 2002, 2003 by lsi logic corporation. all rights reserved. 7.13 flash rom write timings 7-10 7.14 alphanumeric pad listing by pbga position 7-14 7.15 alphanumeric pad listing by signal name 7-16 7.16 maximum allowable ambient temperature vs. air?w 7-19 a.1 LSIFC929X multifunction pci registers a-1 a.2 LSIFC929X host interface registers a-3 b.1 reference speci?ations b-1
LSIFC929X dual channel fibre channel i/o processor technical manual 1-1 copyright 2002, 2003 by lsi logic corporation. all rights reserved. chapter 1 introduction this chapter provides an overview of the LSIFC929X dual channel fibre channel i/o processor. the chapter contains the following sections: ? section 1.1, ?verview ? section 1.2, ?eneral description ? section 1.3, ?ardware overview ? section 1.4, ?nitiator operations ? section 1.5, ?arget operations ? section 1.6, ?iagnostics 1.1 overview the LSIFC929X is a high-performance, cost-effective, dual channel fibre channel (fc) i/o processor. it represents the latest system level integration technology in intelligent i/o processors from lsi logic. the storage area network (san) environment is fully supported with both fibre channel protocol (fcp) for scsi and lan/ip. 1.1.1 hardware features the LSIFC929X supports the following list of hardware features: ? highly integrated, full duplex, dual channel fc i/o processor ? integrated 2 gbit/s dual channel fc serial link ? 64-bit/66 mhz host pci bus and 133 mhz pci-x bus (both are backward compatible with 32-bit/33 mhz) ? integrated bit error rate (ber) link testing ? 32-bit arm risc processor
1-2 introduction copyright 2002, 2003 by lsi logic corporation. all rights reserved. ? intelligent, high-performance context management ? synchronous sram (ssram) external memory interface ? full simultaneous target and initiator operations ? implementation of common message passing interface (mpi) ? firmware support for concurrent host commands 1000 concurrent commands with 1 mbyte sram (default) 2000 concurrent commands with 2 mbytes sram 4000 concurrent commands with 4 mbytes sram ? pc2001 compliant ? peripheral component interface (pci) 2.2 compliant ? jtag debug interface ? 456-pin plastic ball grid array (pbga) 1.1.2 fc features the LSIFC929X supports the following list of fc features: ? class 2 and class 3 support (with optional con?med delivery) ? bb credit of 16, alternate login of 1 (each channel) ? fc-ph compliance ? fc-al 7.0 compliance ? fc-fcp, fc-plda compliance ? fc-fla compliance ? fca-ip, ietf-ipfc compliance ? nl_port (arbitrated loop) ? n_port (point-to-point) ? fl_port (public loop attach) ? f_port (fabric attach) ? autonegotiation between link speeds under ?mware control; provides automatic interoperability between 1 gbit/s and 2gbit/s links (independent for each channel)
overview 1-3 copyright 2002, 2003 by lsi logic corporation. all rights reserved. 1.1.3 software features the LSIFC929X supports the following list of software features: ? fusion-mpt drivers ? optimum server i/o pro?e with low cpu utilization ? optimum workstation i/o pro?e with maximum i/o performance ? diagnostic capability ? host driver support for failover and load balancing ? san storage management 1.1.4 os support the LSIFC929X supports the following list of operating systems: ? windows 2000 ? windows nt 4.0 sp4 and windows nt 5.0 ? windows xp ? netware 4.11 and 5.0 ? unixware 2.12 and gemini ? solaris 2.6, 2.7?86 ? solaris sparc ? linux susi, turbolinux, and red hat linux 1.1.5 targeted applications the LSIFC929X targets the following list of key applications: ? sans ? storage virtualization ? server clustering environments ? embedded raid ? low cost pci-x/fc host adapters ? host main boards ? routers and bridges
1-4 introduction copyright 2002, 2003 by lsi logic corporation. all rights reserved. 1.2 general description the LSIFC929X dual channel fc i/o processor is a high-performance, intelligent i/o processor (iop) that simultaneously supports mass storage and ip protocols on a full duplex, 2 gbit/s fc link. the sophisticated design and local memory architecture work together to reduce the host cpu and pci bandwidth required to support fc i/o operations. from the host cpu perspective, the LSIFC929X manages the fc link at the exchange level for mass storage (fcp) protocols. the LSIFC929X supports multiple i/o requests per host interrupt in most applications. from the fc link perspective, the LSIFC929X is a highly ef?ient nl_port supporting point-to-point, public and private loop topologies, and the fc switch/attach topology de?ed under the ansi x3t11 fc-fs standard. the LSIFC929X uniquely supports fc environments where independent, full duplex transmission is required for maximum fc link ef?iency. special attention has been given to the design to accelerate context switching and link utilization. the LSIFC929X includes a 64-bit, 66 mhz host pci interface and a 133 mhz pci-x interface to the host environment. the host interface minimizes the amount of time spent on the pci bus for nondata moving activities such as initialization, command, and error recovery. in addition, the host interface has inherent ?xibility to support the oem implementation tradeoffs between cpu, pci-x, and i/o bandwidth. the high level of integration in the LSIFC929X controller enables low cost fc implementations. figure 1.1 shows a typical implementation incorporating the LSIFC929X controller.
general description 1-5 copyright 2002, 2003 by lsi logic corporation. all rights reserved. figure 1.1 LSIFC929X typical implementation 1.2.1 multifunction pci-x coupled with the dual channel operation, the LSIFC929X adds multifunction capability on the pci-x bus. this capability allows the host to see two distinct ?hannels or host adapters. each channel provides full, concurrent support for fcp initiator, target, and lan protocols. 1.2.2 autospeed negotiation backward compatibility with 1 gbit/s fc devices is maintained through autospeed negotiation. after a power-on, loss of signal, or loss of word synchronization for longer than the r_t_tov time-out, the LSIFC929X performs this operation to determine whether a point-to-point device or all of the devices on a link are either 1 gbit/s or 2 gbit/s devices, and it automatically con?ures itself to be compatible with the devices on the link. 1.2.3 autotopology negotiation the LSIFC929X maintains compatibility with private loop, public loop, and point-to-point topologies through autotopology negotiation. the LSIFC929X performs this operation to determine the type of attached link, and automatically configures each LSIFC929X port to the current port type. LSIFC929X integrated transceiver memory controller 2 2 serial eeprom (8 kbyte min.) flash rom (1 mbyte) ssram (1 mbyte min.) clock (106 mhz) 32 pci-x bus 32/64 integrated transceiver 2 2 fc channel 0 fc channel 1 support components
1-6 introduction copyright 2002, 2003 by lsi logic corporation. all rights reserved. 1.2.4 failover and load balancing the LSIFC929X supports two pci-x functions and two fc ports, which improves performance and provides a redundant path in high-availability systems that require failover capabilities. in case of a link failure, the LSIFC929X architecture allows the os driver to support automatic failover without the need for LSIFC929X intervention. load balancing also can be provided in the host driver to partition the i/o workload across each channel of the LSIFC929X. 1.3 hardware overview in todays fast growing san, storage virtualization, server/workstation, and raid storage systems marketplaces, higher levels of performance, scalability, and reliability are required to stay competitive. the LSIFC929X provides the performance and ?xibility to meet future fc connectivity requirements. the LSIFC929X and lsi logic software drivers provide superior performance and lower host cpu overhead than other competitive solutions. because of its high level of integration and streamlined architecture, the LSIFC929X provides the highest level of performance in a more cost effective fc solution. figure 1.2 shows the functional block diagram for the LSIFC929X. the architecture maximizes performance and ?xibility by deploying ?ed gates in critical performance areas and utilizing multiple arm risc processors (two for context management and one for the i/o processor). each of the major blocks is described brie?.
hardware overview 1-7 copyright 2002, 2003 by lsi logic corporation. all rights reserved. figure 1.2 LSIFC929X functional block diagram 1.3.1 pci/pci-x interface the LSIFC929X uses a 64-bit (33 mhz, 66 mhz, or 133 mhz) pci/pci-x interface or a 32-bit (33 mhz, 66 mhz, or 133 mhz) pci/pci-x interface. in addition, support is provided for dual address cycle (dac), pci-x power management, subsystem vendor id, vendor product data (vpd), and message signaled interrupt (msi). 1.3.2 32-bit memory controller the memory controller provides access to flash rom and 32-bit synchronous sram and nonvolatile sram (nvsram). it supports both interleaved and noninterleaved con?urations up to a maximum of 4 mbytes of synchronous sram. a general purpose memory expansion bus supports up to 1 mbyte of flash rom. 1.3.3 i/o processor the LSIFC929X uses a 32-bit arm risc processor to control all system interface and message transport functionality. this frees the host cpu for other processing activity and improves overall i/o performance. the risc processor and associated ?mware can manage an i/o from start to ?ish without host intervention. the risc processor also manages the message passing interface. LSIFC929X i/o processor fc xcvr ssram 400 mbps 64-bit 133 mhz pci-x 32-bit memory controller pci-x interface 2 gbit/s fc 400 mbps 2 gbit/s fc xmtr context rcvr link system interface fc xcvr xmtr context rcvr controller link controller
1-8 introduction copyright 2002, 2003 by lsi logic corporation. all rights reserved. 1.3.4 system interface the system interface ef?iently passes messages between the LSIFC929X and other i/o agents. it consists of four hardware fifos for the message queuing lists: request free, request post, reply free, and reply post. control logic for the fifos is provided within the LSIFC929X system interface with messages stored in external memory. 1.3.5 integrated 2 gbit/s transceivers the LSIFC929X implements gigablaze 2 gbit/s transceivers. gigablaze is backward-compatible with 1 gbit/s systems, using a ?mware-implemented ?utospeed negotiation for automatic compatibility between 1 gbit/s and 2 gbit/s links. the integrated 2 gbit/s transceivers provide a fc-compliant physical interface for cost conscious and real estate limited applications. 1.3.6 link controllers the integrated link controller is fc-al-2 (rev. 7.0) compatible and performs all link operations. the controller monitors the link state and strictly adheres to the loop port state machine, ensuring maximum system interoperability. the link controller interfaces to the integrated transceiver. 1.3.7 datapath the transmitter builds sequences based on context information and transmits resulting frames to the fc link using the link controller. each transmitter includes two 2 kbyte buffers to support frame payloads. the receivers accept frame data from the link controller and dmas the encapsulated information to local or system memory. each receiver contains sixteen 2112-byte buffers that support a bb credit of up to sixteen or an alternate login bb credit of 1 on each channel. 1.3.8 context managers the LSIFC929X uses an arm risc processor in each channel to support i/o context swap to external memory and fcp management for both initiator and target applications. context operations include support for transmit and resource queue management, as well as scatter/gather list management.
initiator operations 1-9 copyright 2002, 2003 by lsi logic corporation. all rights reserved. 1.4 initiator operations the LSIFC929X autonomously handles fcp exchanges upon request from the host. the LSIFC929X generates appropriate sequences and frames necessary to complete the request and provides feedback to the host on the status of the request. 1.5 target operations the LSIFC929X provides for general purpose target functions such as those required for front-end raid applications. 1.6 diagnostics the LSIFC929X provides the capabilities to do a simpli?d ?ink check ber test on the link for diagnostic purposes. in a special test mode the controller can transmit and verify a programmed data pattern for link evaluation.
1-10 introduction copyright 2002, 2003 by lsi logic corporation. all rights reserved.
LSIFC929X dual channel fibre channel i/o processor technical manual 2-1 copyright 2002, 2003 by lsi logic corporation. all rights reserved. chapter 2 fibre channel overview this chapter provides general overview information on fibre channel (fc). the chapter contains the following sections: ? section 2.1, ?ntroduction ? section 2.2, ?c layers ? section 2.3, ?rames ? section 2.4, ?xchanges ? section 2.5, ?c ports ? section 2.6, ?c topologies ? section 2.7, ?lasses of service
2-2 fibre channel overview copyright 2002, 2003 by lsi logic corporation. all rights reserved. 2.1 introduction fc is a high-performance, hybrid interface. it is both a channel and a network interface that contains network features to provide the required connectivity, distance, protocol multiplexing, as well as traditional channel features to retain the required simplicity, repeatable performance, and guaranteed delivery. popular industry standard networking protocols such as internet protocol (ip) and channel protocols such as small computer system interface (scsi) have been mapped to the fc standard. the fc structure is defined by five functional layers. these layers, shown in figure 2.1 , define the physical media and transmission rates, encoding scheme, framing protocol and flow control, common services, and the upper level protocol (ulp) interfaces. figure 2.1 fc layers ip escon hippi ipi-3 fcp 8496 4248 2124 1062 upper layer protocol (ulp) common services ?for example, ...striping (not de?ed) framing protocol/flow control 8b/10b encode/decode system interface fc-4 fc-3 fc-2 fc-1 fc-0 mbits/s (full duplex) fc-ph-2 mbytes/s 100 200 400 800 behaviors logical layers physical layers
fc layers 2-3 copyright 2002, 2003 by lsi logic corporation. all rights reserved. 2.2 fc layers the lowest layer, fc-0, is the media interface layer. it de?es the physical characteristics of the interface. it includes transceivers, copper-to-optical transducers, connectors, and any other associated circuitry necessary to transmit or receive at 1062 or greater mbit/s rates over copper or optical cable. the fc-1 layer de?es the 8b/10b encoding/decoding scheme, the transmission protocol necessary to integrate the data and transmit clock, and the receive clock recovery. implementation of this layer is usually divided between the hardware implementing the fc-0 layer in a transceiver, and the protocol device that implements the fc-2 layer. speci?ally, the fc-0 transceivers can include the clock recovery circuitry while the 8b/10b encoding/decoding is provided in the protocol device. the fc-2 layer de?es the rules for the signaling protocol and describes transfer of the frames, sequences, and exchanges. the meaning of the data being transmitted or received is transparent to the fc-2 layer. however, the context between any given set of frames is maintained at the fc-2 layer through the sequence and exchange constructs. the framing protocol creates the constructs necessary to form frames with the data being packetized within the payload of each frame. the fc-3 layer provides common services that span multiple n_ports (refer to section 2.5, ?c ports, on page 2-7 for details). some of these services include striping, hunt groups, and multicasting. all of these services allow a single port or fabric to communicate to several n_ports at one time. the fc-4 layer is the top layer de?ed in the fc. the fc-4 layer provides a seamless integration of existing standards. it speci?s the mapping of ulps to the layers below. some of these ulps include scsi and ip. each of these ulps is de?ed in its own ansi document.
2-4 fibre channel overview copyright 2002, 2003 by lsi logic corporation. all rights reserved. 2.3 frames there are two types of frames used in fc: link control frames and data frames. link control frames, which contain no payload, are ?w control responses to data frames. an example of a link control frame is the ack frame. figure 2.2 link control frame a data frame is any frame that contains data in the payload ?ld. an example of a data frame is the login frame. figure 2.3 data frame in fc, an ordered set is a group of four 10-bit characters that provide low level link functions, such as frame demarcation and signaling between two ends of a link. all frames start with a start-of-frame (sof) and end with an end-of-frame (eof) ordered set. each frame contains at least a 24-byte header de?ing such things as destination and source id, class of service and type of frame (for example, fcp or fc-le). the biggest ?ld within a frame can be the payload ?ld. if the frame is a link control frame, then there is no payload. if it is a data frame, then the frame contains a payload ?ld of up to 2112 bytes. finally, the frame includes a crc ?ld used for detection of transmission errors, followed by the eof ordered set. start of frame (4 bytes) frame header (24 bytes) crc (4 bytes) end of frame (4 bytes) start of frame (4 bytes) frame header (24 bytes) crc (4 bytes) end of frame (4 bytes) data field (optional headers payload ) (0 to 2112 bytes) and
exchanges 2-5 copyright 2002, 2003 by lsi logic corporation. all rights reserved. 2.4 exchanges figure 2.4 outlines the fc hierarchical data structures. at the most elemental level, four 8b/10b encoded characters make up an fc word. an fc frame is a collection of fc words. an fc sequence is made up of one or more frames, and a fc exchange is made up of one or more sequences. figure 2.4 exchange to character the following discussion illustrates an exchange by considering a typical parallel scsi i/o. in parallel scsi, several phases make up the i/o. these phases include command, data, message, and status. using the fcp for the scsi ulp, these phases can be mapped into the other lower fc layers. figure 2.5 shows the components that make up the fcp exchange. seq 1 seq 2 seq 4 seq n exchange frame 1 frame 2 frame 4 frame n seq 3 frame 3 sof header data crc eof frame k28.5 d21.5 d23.0 word d23.0 0 character 0 1 1 1 1 1 0 1 0
2-6 fibre channel overview copyright 2002, 2003 by lsi logic corporation. all rights reserved. figure 2.5 fcp exchange figure 2.6 shows how the exchange ?ws between the initiator and target. the initiator starts the fcp exchange by sending a command sequence containing one frame to the target. the frame payload contains the command descriptor block (cdb). the target then responds with a data delivery request sequence containing one frame. the payload of this frame contains a xfer_rdy response. when the initiator receives the targets response, it begins to send the data sequence(s), which may contain one or more frames. this is analogous to parallel scsi data_out phase. when the target has received the last frame of the data sequence(s), it sends a response sequence containing one frame to the initiator, thus concluding the fcp exchange. cmdseq datareqseq fcp exchange frame 1 frame 2 frame n frame 1 responseseq dataseq frame 1 frame 1
fc ports 2-7 copyright 2002, 2003 by lsi logic corporation. all rights reserved. figure 2.6 write event trellis 2.5 fc ports fc devices are called nodes. each node has at least one port to provide access to other ports in other nodes. the ?ort is the hardware entity within a node that performs data communications over the fc link. various types of ports are de?ed within the fc standard, based on the location of the port and the topology associated with it. the most commonly used ports are n_ports, nl_ports, f_ports, and fl_ports. these types of ports appear in figure 2.7 , figure 2.8, and figure 2.9 . 2.6 fc topologies topologies are de?ed, based on the capability and the presence or absence of fabric between the n_ports: ? point-to-point topology ? fabric topology ? arbitrated loop topology fc-ph protocols are topology-independent. attributes of a fabric may restrict operation to certain communication models. initiator fabric cmd seq data seq frame 1 data seq frame 2 data seq frame n data req seq rsp seq target
2-8 fibre channel overview copyright 2002, 2003 by lsi logic corporation. all rights reserved. 2.6.1 point-to-point topology the topology shown in figure 2.7 , in which communication between n_ports occurs without the use of fabric, is de?ed as point-to-point. figure 2.7 point-to-point topology 2.6.2 fabric topology figure 2.8 illustrates multiple n_ports interconnected by a fabric. this topology uses the destination_identi?r (d_id) embedded in the frame header to route the frame through a fabric to the desired destination n_port. figure 2.8 fabric topology 2.6.3 arbitrated loop topology the arbitrated loop topology permits 2?27 l_ports to communicate without the use of a fabric, as in fabric topology. the arbitrated loop supports a maximum of one point-to-point circuit at a time. when two l_ports are communicating, the arbitrated loop topology supports simultaneous, symmetrical bidirectional ?w. figure 2.9 illustrates two independent arbitrated loop configurations, each with multiple l_ports attached. each line in the figure between l_ports represents a single fibre. the lower configuration shows an arbitrated loop composed of three nl_ports and one fl_port (a public loop). n_port b n_port a fabric f_port n_port n_port f_port n_port f_port f_port n_port
classes of service 2-9 copyright 2002, 2003 by lsi logic corporation. all rights reserved. figure 2.9 arbitrated loop topology 2.7 classes of service there are several classes of service in fc. the different classes are distinguished from each other in three ways: by the level of guarantee for data being delivered, the order in which data is delivered, and how data ?w control is maintained. class 1 is a dedicated connection between two n_ports. the data delivered is guaranteed with a required acknowledgement frame (ack), which a class 1 device uses for flow control. all frames are received in order. class 2 is a connectionless class. the data delivered is guaranteed with an ack frame. the frames can be received out of order. class 2 uses both ack frames and the r_rdy ordered set for ow control. class 3 is also a connectionless class (the data being delivered is not guaranteed). the frames can be received out of order. class 3 uses only the r_rdy ordered set for ow control. nl_port nl_port nl_port nl_port private loop fabric element fl_port nl_port nl_port nl_port public loop
2-10 fibre channel overview copyright 2002, 2003 by lsi logic corporation. all rights reserved. intermix is an enhancement of class 1 service. a dedicated class 1 connection may waste fabric bandwidth while frames are not being transmitted or received between two n_ports. to recover some of this bandwidth, intermix allows class 2 and class 3 frames to be transmitted/received between class 1 frames. n_ports advertising intermix capability must be capable of receiving class 2 and class 3 frames from other n_ports while maintaining the original class 1 link.
LSIFC929X dual channel fibre channel i/o processor technical manual 3-1 copyright 2002, 2003 by lsi logic corporation. all rights reserved. chapter 3 LSIFC929X overview this chapter provides a general description of the LSIFC929X dual channel fibre channel i/o processor ?mware. the chapter contains the following sections: ? section 3.1, ?ntroduction ? section 3.2, ?essage interface ? section 3.3, ?csi message ? section 3.4, ?an message ? section 3.5, ?arget message ? section 3.6, ?upport components 3.1 introduction the lsi logic LSIFC929X connects a host to a high speed fc link. the fcp ansi standard, fc private loop direct attach, and fabric loop attach profiles are supported with a sophisticated firmware implementation. all profiles, specifications, and interoperability maintained by the LSIFC929X are listed in appendix b, ?eference specifications . although optimized for a 64-bit pci-x interface to communicate with the system cpu(s) and memory, the LSIFC929X also supports a 32-bit peripheral component interface (pci) environment. the system interface to the LSIFC929X minimizes the amount of pci-x bandwidth required to support i/o requests. a packetized message passing interface reduces the number of single cycle pci bus cycles. all fc data traf? on the pci-x bus occurs with zero wait state bursts across the pci-x bus.
3-2 LSIFC929X overview copyright 2002, 2003 by lsi logic corporation. all rights reserved. the intelligent LSIFC929X architecture allows the system to specify i/os at the command level. the LSIFC929X manages i/os at the frame, sequence and exchange level. error detection and i/o retries are also handled by the LSIFC929X, allowing the system to of?ad part of the exception handling work from the system driver. data flows the LSIFC929X uses a 64-bit (33 mhz, 66 mhz, or 133 mhz) pci-x interface to pass control and data information between the system and the protocol controller. this interface is managed by the pci- x interface block, as shown in figure 3.1 . it is backward compatible with 32-bit/33 or 66 mhz buses. figure 3.1 LSIFC929X block diagram for incoming serial data, the physical link transfers the data to link control using the gigablaze integrated transceiver. the link controller analyzes the received frame, and if appropriate, it passes the frame to the receiver. the receiver strips off the frame header and places it in a separate header buffer while the data in the frame payload is placed in a data buffer. the frame receiver uses the receive context manager to manage the order and priority of the received frame. the data contained in the receiver buffers is associated with a specific scatter/gather entry and passed on to the pci-x interface. the data also requests the pci-x bus and bursts the data into system memory. the i/o processor (iop), with its ?mware, provides the translation from fc speci? protocols to the high level block storage, scsi, and lan message interface. this translation allows the LSIFC929X to be i/o processor fc xcvr ssram 400 mbps 64-bit 133 mhz pci-x 32-bit memory controller external pci-x interface 64-bit 2 gbit/s fc 400 mbps 2 gbit/s fc xmtr context rcvr link system interface fc xcvr xmtr context rcvr link
message interface 3-3 copyright 2002, 2003 by lsi logic corporation. all rights reserved. integrated into the system as if it were a native parallel scsi or lan device, hiding all fc-unique characteristics. internal communication between the iop and the context manager occurs over an internal bus, which also is connected to an external memory controller. the iop uses the external memory controller to access local memory. this memory contains the ?mware, as well as the dynamic data structures used by the ?mware. 3.2 message interface the LSIFC929X system interface is a high-performance, packetized, mailbox architecture that leverages the intelligence in the LSIFC929X to minimize traf? on the pci-x bus. there are two basic constructs in the message interface. the ?st construct, the message, communicates between the system and the LSIFC929X. messages are moved between the system(s) and the LSIFC929X using the second construct, a transport mechanism. 3.2.1 messages the LSIFC929X uses two types of messages to communicate with the system. request messages are created by the system to ?equest an action by the LSIFC929X. reply messages are used by the LSIFC929X to send status information back to the system. request message data structures are up to 128 bytes in length. the message includes a message header and a payload. the header includes information to uniquely identify the message. the payload is speci? to the request itself, and is unique for scsi, lan, and target messages. for more information regarding the details of the message format, refer to the fusion-mpt tm message passing interface speci?ation .
3-4 LSIFC929X overview copyright 2002, 2003 by lsi logic corporation. all rights reserved. 3.2.2 message flow before requests can be posted to the LSIFC929X, the system must allocate and initialize a pool of message frames, and provide a mechanism to assign individual message frames on a per-request basis. the host also must provide one message frame per target lun, and prime the reply free fifos for each function with the physical address of these message frames. when allocation has been completed, requests flow from the host to the LSIFC929X, as represented below and in figure 3.2 . 1. the host driver receives an i/o request from the operating system. 2. the host driver allocates a system message frame (smf) and builds an i/o request message within the smf. the allocation method is the responsibility of the host driver. 3. the host driver creates the message frame descriptor (mfd) and writes the mfd to the request post fifo. 4. the i/o controller (ioc) reads the mfd from the request post fifo and dmas the request to a local message frame. 5. the ioc sends the appropriate fibre channel request and subsequently receives the reply from the target. if the i/o status is successful, the ioc writes the messagecontext value, plus turbo reply bits, to the reply post fifo, which automatically generates a system interrupt. if the i/o status is not successful, the ioc pops a reply message frame from the reply free fifo and generates a reply message in the reply message frame. the ioc then writes the system physical address of the reply message frame to the reply post fifo, which generates a system interrupt. 6. the host driver receives a system interrupt and reads the reply register. if there are no posted messages, the system reads the value 0xffffffff. 7. the host driver responds to the operating system appropriately. 8. if the i/o status is not successful, the host driver returns it to the reply free fifo.
message interface 3-5 copyright 2002, 2003 by lsi logic corporation. all rights reserved. figure 3.2 LSIFC929X message flow host driver reply register ioc 1 2 n 3 message pci-x bus 2 operating system frames 7 1 8 1 2 n reply free 1 2 n reply post 1 2 n request post 5 request register 3 6 3 5 4 6 mfd system fifo fifo fifo
3-6 LSIFC929X overview copyright 2002, 2003 by lsi logic corporation. all rights reserved. 3.3 scsi message the scsi message interface provides the most direct interface for block-oriented storage media. this includes disk drives and tape devices. the scsi i/o path translates a scsi command descriptor block (cdb) into a fibre channel protocol (fcp) exchange. all fc device and target discovery operations are managed completely within the LSIFC929X. fc target devices are assigned a logical (bus, target id) identi?r, and are accessed by the system as if they were parallel scsi devices. the system is responsible for scanning the target devices and identifying luns on the target devices. in general, the system is responsible for retrying operations at an i/o request level. the LSIFC929X is responsible for responding to bus protocol-speci? errors and exceptions and retrying bus sequences within the scope of an i/o operation. the system is also responsible for maintaining a timer for scsi i/o operations if this is required by the host system. the host driver may use the provided scsi task management functions to terminate one or more i/o operations when a timeout occurs. for details regarding the scsi message class, refer to the fusion-mpt tm message passing interface speci?ation . 3.4 lan message the LSIFC929X provides a lan message interface that supports the system transfer communications protocol (tcp) or user datagram protocol (udp) network driver stack, providing media access controller (mac) level communication between fc ports. the typical network driver stack in the system consists of a socket driver with a transport driver interface, supported by tcp or udp and ip drivers, and a hardware abstraction layer interface to the LSIFC929X. the tcp driver provides data buffer segmentation. the ip driver provides mtu segmentation, adds a header and checksum to the tcp data, and maps each fibre channel mac port address to an ieee standard address. acks are required at the tcp driver to ensure all segments of the data block are transmitted/received.
lan message 3-7 copyright 2002, 2003 by lsi logic corporation. all rights reserved. the lan message interface also may be used by proprietary protocol stacks in the host, as shown in figure 3.3 . in this environment, the LSIFC929X transmits and receives data between fc nodes without regard to data content. for details regarding the lan message class, refer to the fusion-mpt tm message passing interface speci?ation . figure 3.3 lan protocol stack ieee address ip header w/checksum tcp header w/checksum tcp data (var) applications sockets interface transport driver interface transmission control protocol internet protocol driver driver interface hal pci LSIFC929X lan class fc framer fc ip header w/checksum tcp header w/checksum tcp data (var) tcp header w/checksum tcp data (var) 16 kbytes mac header fc sequence/frame paged data
3-8 LSIFC929X overview copyright 2002, 2003 by lsi logic corporation. all rights reserved. 3.5 target message the target interface allows the LSIFC929X to be used as the system interface for fc bridge controllers. the LSIFC929X provides an fcp exchange level message interface that routes commands to the system. the system identi?s the appropriate data, and passes a scatter gather list (sgl) to the LSIFC929X describing the data to transfer. a single target message directs the LSIFC929X to send a xfer_rdy, as needed, and to transfer data and an fcp response. target speci? process login/logout is managed by the system. refer to the fusion-mpt tm message passing interface speci?ation for details on the target message class. 3.6 support components the memory controller block within the LSIFC929X provides access to external local memory resources required to manage fcp. the following sections provide guidance in choosing the support components necessary for a fully functional implementation using the LSIFC929X. figure 3.4 shows an LSIFC929X typical implementation diagram.
support components 3-9 copyright 2002, 2003 by lsi logic corporation. all rights reserved. figure 3.4 LSIFC929X typical implementation 3.6.1 ssram memory the primary function of this memory is to store data structures used by the LSIFC929X to manage exchanges and transmit and receive queues. the ssram memory also stores part of the run time image of the LSIFC929X firmware, such as initialization and error recovery code. the mainline code is stored within the internal lram for performance reasons. the LSIFC929X uses a 32-bit, nonmultiplexed memory bus to access the ssram. this memory bus has the capability to address up to 4 mbytes of ssram. the LSIFC929X ?mware also supports optional byte wide parity error detection. this con?urable option is speci?d as a serial eeprom parameter. the amount of ssram (1 mbyte) determines the maximum number of outstanding request messages (1024). this roughly equates to the maximum number of outstanding i/o requests pending in the LSIFC929X. LSIFC929X integrated transceiver memory controller 2 2 serial eeprom (8 kbyte min.) flash rom (1 mbyte) clock (106 mhz) 32 pci-x bus 32/64 integrated transceiver 2 2 fc channel 0 fc channel 1 support components ssram (1 mbyte min.) memory
3-10 LSIFC929X overview copyright 2002, 2003 by lsi logic corporation. all rights reserved. 3.6.2 flash rom the memory controller in the LSIFC929X also manages an optional flash rom. if present, the flash rom stores the firmware for the LSIFC929X, and if desired, the intel bios and/or solaris open boot bios software. if the flash rom is not used, then the host platform is responsible for downloading the iop firmware to the LSIFC929X through the pci-x interface. the LSIFC929X supports a simple register handshake interface for firmware download. firmware may be directly written to the LSIFC929X internal memory and external ssram through this interface. details of this implementation are available in the fusion-mpt tm message passing interface speci?ation . flash rom is optional for the LSIFC929X, but it is required for applications that require intel or solaris bios software. the flash rom is accessed using the upper 8 bits of the memory interface. if a flash rom is to be used, then it should have a capacity of 1 mbyte with a maximum access time of 150 ns. refer to the fusion-mpt tm message passing interface speci?ation for details on the programming of the flash rom. 3.6.3 serial eeprom the serial eeprom stores nonvolatile data for the LSIFC929X, such as the world wide name, vpd, and other vendor-speci? information. the seeprom data is programmed by the ?mware, so the ?mware must be downloaded and running before the seeprom is programmed. the required minimum size of the seeprom is 8 kbytes.
LSIFC929X dual channel fibre channel i/o processor technical manual 4-1 copyright 2002, 2003 by lsi logic corporation. all rights reserved. chapter 4 signal descriptions this chapter contains signal descriptions for the LSIFC929X. a slash (/) indicates an active low signal, i/o = bidirectional signal, i = input signal, o = output signal, t/s = 3-state, and s/t/s = sustained 3-state. the chapter contains the following sections: ? section 4.1, ?ci/pci-x interface ? section 4.2, ?ibre channel interface ? section 4.3, ?emory interface ? section 4.4, ?on?uration and miscellaneous ? section 4.5, ?est and i/o processor debug ? section 4.6, ?ower and ground figure 4.1 on page 4-2 is a functional signal grouping for the chip.
4-2 signal descriptions copyright 2002, 2003 by lsi logic corporation. all rights reserved. figure 4.1 LSIFC929X functional signal grouping tx0+ tx0- tx1+ tx1- rx1- rtrim lipreset/ fault0/ fault1/ odis0 odis1 bypass0/ bypass1/ tck trst/ tdi tdo tms_chip tms_ice test[9] test[8:0] LSIFC929X fibre channel interface test and i/o processor mode[7:0] gpio[5:0] led[4:0]/ scl sda zz flashcs/ ramcs/ ma[21:0] md[31:0] mp[3:0] adv/ adsc/ bwe[3:0]/ mwe[1:0]/ moe[1:0]/ mclk ad[63:0] gnt/ c_be[7:0]/ frame/ trdy/ stop/ serr/ intb/ rst/ req/ idsel irdy/ devsel/ perr/ pa r req64/ ack64/ par64 pciclk memory interface pci-x interface con?uration inta/ rx0- rx1+ rx0+ rxlos0 rxlos1 moddef0[2:0] moddef1[2:0] refclk and miscellaneous enum/ 64en/ switch hotswapen/ debug bzrset bzvdd
pci/pci-x interface 4-3 copyright 2002, 2003 by lsi logic corporation. all rights reserved. 4.1 pci/pci-x interface table 4.1 lists the pci/pci-x interface signals. table 4.1 pci/pci-x interface signal i/o bga pad no. pad type description pciclk i v1 5 v tol in clock . refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . rst/ i u3 5 v tol in reset . refer to the pci local bus speci?ation, version 2.2, and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . gnt/ i/o u4 5 v tol bidir pci grant . refer to the pci local bus speci?ation, version 2.2, and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . req/ i/o v2 5 v tol bidir pci request . refer to the pci local bus speci?ation, version 2.2, and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . req64/ i/o ad14 5 v tol bidir pci request64 . refer to the pci local bus speci?ation, version 2.2, and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . ack64/ s/t/s ae14 5 v tol bidir pci acknowledge64 . refer to the pci local bus speci?ation, version 2.2, and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description .
4-4 signal descriptions copyright 2002, 2003 by lsi logic corporation. all rights reserved. ad[63:0] t/s ae16, ae17, ad17, ac17, af18, ae18, ad18, af19, ac19, ae19, af20, ae20, ac20, af21, ae21, ad21, af22, ac21, ae22, ad22, af23, ae23, ae24, ae25, ad25, ad26, ad24, ac25, aa26, ab24, aa23, y23, v3, w1, w2, w5, y1, y2, y4, ab1, aa4, w4, ab2, ac1, ac3, ad2, af6, ae3, ac8, ae8, af8, ad9, ae9, af10, ae10, ac10, ac11, ae12, af13, ac12, ae13, ad13, ac15, ac13 5vtol bidir pci address and data . refer to the pci local bus speci?ation, version 2.2, and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . c_be[7:0]/ t/s ac14, af15, ae15, af14, aa2, ae4, af7, ad10 5vtol bidir pci command and byte enables . refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . idsel i/o aa3 5 v tol bidir pci initialization device select . refer to the pci local bus speci?ation, version 2.2, and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . frame/ s/t/s af3 5 v tol bidir pci cycle frame . refer to the pci local bus speci?ation, version 2.2, and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . table 4.1 pci/pci-x interface (cont.) signal i/o bga pad no. pad type description
pci/pci-x interface 4-5 copyright 2002, 2003 by lsi logic corporation. all rights reserved. irdy/ s/t/s ae5 5 v tol bidir pci initiator ready . refer to the pci local bus speci?ation, version 2.2, and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . trdy/ s/t/s af4 5 v tol bidir pci target ready . refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . devsel/ i/o ac6 5 v tol bidir pci device select . refer to the pci local bus speci?ation, version 2.2, and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . stop/ s/t/s ad6 5 v tol bidir pci stop . refer to the pci local bus speci?ation, version 2.2, and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . perr/ s/t/s ae6 5 v tol bidir pci parity error . refer to the pci local bus speci?ation, version 2.2, and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . serr/ i/o af5 5 v tol bidir pci system error . refer to the pci local bus speci?ation, version 2.2, and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . par t/s ae7 5 v tol bidir pci parity . refer to the pci local bus speci?ation, version 2.2, and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . par64 i/o af16 5 v tol bidir pci parity64 . refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . inta/ i/o t4 5 v tol bidir pci interrupt a . refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . table 4.1 pci/pci-x interface (cont.) signal i/o bga pad no. pad type description
4-6 signal descriptions copyright 2002, 2003 by lsi logic corporation. all rights reserved. intb/ i/o t2 5 v tol bidir pci interrupt b . refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description . enum/ i/o p4 5 v tol bidir pci enumeration interrupt . this signal must be asserted by a hot swap capable card immediately after insertion and during removal. this signal noti?s the system host either that a board has been freshly inserted or that one is about to be extracted, and informs the system host that the con?uration of the system has changed. the system host then can perform any necessary maintenance such as installing a device driver upon board insertion, or quiescing a device driver and the board, prior to extracting the board. 64en/ i/o p1 5 v tol bidir pci pci bus width enable . this signal indicates the width of the bus when hot swap capability is enabled. switch i r1 5 v tol in insertion/deassertion indicator . this signal is an input to the LSIFC929X to signal the insertion or impending extraction of a board. this signal causes the assertion of enum/. the operator normally activates the switch (actuator), waits for the illumination of the led, and then extracts the board. hotswapen/ i/o t1 5 v tol in hot swap enable . when this signal is low, the LSIFC929X is con?ured to conform to hot swap protocol. this includes changing the bus width detection method, the addition of con?uration registers, and support for the enum/, blueled/ and switch pins. gpio[2] (blueled/) i/o k1 3.3 v bidir 8 ma with pull-up gpio[2] (blueled/) . this signal drives a blue led that is mounted on the front of hot swap capable host adapters. this signal indicates that the system software has been placed in a state for orderly extraction of the board. refer also to the gpio[2] pin description in table 4.4 on page 4-14 for details on other operational capabilities of this signal. table 4.1 pci/pci-x interface (cont.) signal i/o bga pad no. pad type description
fibre channel interface 4-7 copyright 2002, 2003 by lsi logic corporation. all rights reserved. 4.2 fibre channel interface table 4.2 lists the fibre channel interface signals. table 4.2 fibre channel interface signal i/o bga pad no. pad type description tx0+ o b10 diff tx transmit differential data (channel0). tx1+ o b15 diff tx transmit differential data (channel1). tx0 ? o a10 diff tx transmit differential data (channel0). tx1 ? o a15 diff tx transmit differential data (channel1). rx0+ i b12 diff rx receive differential data (channel0). rx1+ i b17 diff rx receive differential data (channel1). rx0 ? i a12 diff rx receive differential data (channel0). rx1 ? i a17 diff rx receive differential data (channel1). rtrim i c13 trim resistor . this pin is the analog current reference for the integrated transceiver core. a 2.74 k ?1% resistor should be tied from the rtrim pad to either the rxvdd0 or the rxvdd1 pin . lipreset/ o c14 3.3 v bidir 4ma loop initialization primitive reset . this pin is asserted low when a selective reset is received that is targeted to an alias of this device. this pin is asserted for 1? ms after the last lipr is received. fault0/ i b8 3.3 v ttl input with pull-up electrical fault . this active-low pin indicates that an electrical fault has been detected by the channel0 phy device/module and, if the module has a laser, the laser has been turned off. this pin causes no interrupt or other reaction. it is assumed that a link failure occurs, and that the register bit reporting the value of this pin diagnoses the problem.
4-8 signal descriptions copyright 2002, 2003 by lsi logic corporation. all rights reserved. fault1/ i b19 3.3 v ttl input with pull-up electrical fault . this active-low pin indicates that an electrical fault has been detected by the channel1 phy device/module and, if the module has a laser, the laser has been turned off. this pin causes no interrupt or other reaction. it is assumed that a link failure occurs, and that the register bit reporting the value of this pin diagnoses the problem. odis0 o b7 3.3 v bidir 4ma output disable, channel0. this output, when asserted, disables an external gbic or mia transmitter for channel0. this output also clears a module fault. odis1 o b20 3.3 v bidir 4ma output disable, channel1. this output when asserted disables an external gbic or mia transmitter for channel1. this output also clears a module fault. bypass0/ o d8 3.3 v bidir 4ma bypass . this line is driven low when the LSIFC929X link controller block determines that channel0 of the device is operating in a loop environment and that the device has entered a bypassed mode. this may be caused by an internal request or by a loop primitive generated at another node. bypass1/ o d19 3.3 v bidir 4ma bypass . this line is driven low when the LSIFC929X link controller block determines that channel1 of the device is operating in a loop environment and the device has entered a bypassed mode. this may be caused by an internal request or a loop primitive generated at another node. rxlos0 i a8 3.3 v 4 ma bidir with pull-down received signal loss . this line is driven high, disabling the on-chip receiver, when the gbic for channel0 of the LSIFC929X detects a loss of signal. if enabled through the link control register, this signal becomes an output test strobe. table 4.2 fibre channel interface (cont.) signal i/o bga pad no. pad type description
fibre channel interface 4-9 copyright 2002, 2003 by lsi logic corporation. all rights reserved. rxlos1 i a19 3.3 v 4 ma bidir with pull-down received signal loss . this line is driven high, disabling the on-chip receiver, when the gbic for channel1 of the LSIFC929X detects a loss of signal. if enabled through the link control register, this signal becomes an output test strobe. moddef0[2:0] i d9, a7, e11 3.3 v bidir 8ma with pull-up module identi?rs . gbic and pluggable small form factor (sff) optical module identi?rs (channel0). moddef1[2:0] i e16, a20, d18 3.3 v bidir 8ma with pull-up module identi?rs . gbic and pluggable sff optical module identi?rs (channel1). refclk i c1 3.3 v schmitt input fc reference clock . fc reference clock (106.25 mhz 100 ppm). table 4.2 fibre channel interface (cont.) signal i/o bga pad no. pad type description
4-10 signal descriptions copyright 2002, 2003 by lsi logic corporation. all rights reserved. 4.3 memory interface table 4.3 shows the memory interface signals. table 4.3 memory interface signal i/o bga pad no. pad type description md[31:0] md[31:24] i/o p24, p23, n26, n25, n24, n23, m26, m25, m23, l26, l25, l23, k26, k25, k24, k23, d25, c26, c25, b25, a24, b24, c24, a23, b23, d23, a22, b22, c21, d21, d20, e20 3.3 v bidir 4ma ssram read/write data . md[31:24] are used for the flash rom read/write data. mp[3:0] i/o p25, j24, d26, e19 3.3 v 4ma bidir with pull-up memory parity . byte lane parity is as follows: mp [0]: parity for md[7: 0] mp [1]: parity for md[15: 8] mp [2]: parity for md[23:16] mp [3]: parity for md[31:24] memory parity may be optionally even, odd, or none (not used) as de?ed in the LSIFC929X programming model.
memory interface 4-11 copyright 2002, 2003 by lsi logic corporation. all rights reserved. ma[21:0] i/o ac26, ab26, aa25, y26, y25, w26, w25, w23, v26, v25, v24, u26, u25, u24, u23, t26, t25, t23, r26, r25, r23, r22 3.3 v bidir 4ma ssram/flash rom address . these pins are also used at power-on to provide con?uration information to the LSIFC929X. following are the power-on sense functions of each of the pins: note: ? means the pin is pulled up on reset ? means the pin is pulled down on reset (these pins have internal put-downs) ma[21:18] not applicable for power-on sense ma[17] 1 = keep the iop from booting 0 = enable iop booting following reset ma[16] 1 = channel 1 rxlos1 signal polarity is active low 0 = channel 1 rxlos1 signal polarity is active high ma[15] 1 = channel 0 rxlos0 signal polarity is active low 0 = channel 0 rxlos0 signal polarity is active high ma[14] 1 = fault1/ signal polarity is active high 0 = fault1/ signal polarity is active low ma[13] 1 = fault0/ signal polarity is active high 0 = fault0/ signal polarity is active low ma[12:11] 00 = pci rom size is 256 kbytes 01 = pci rom size is 512 kbytes 10 = pci rom size is 1 mbyte 01 = no rom is present ma[10] 1 = do not report bus as 66 mhz capable 0 = report device as 66 mhz capable ma[9] 1 = report device as not supporting pci 64-bit mode 0 = report device as supporting pci 64-bit mode ma[8] 1 = report device as supporting 66 mhz pci-x 0 = report device as supporting 133 mhz pci-x table 4.3 memory interface (cont.) signal i/o bga pad no. pad type description
4-12 signal descriptions copyright 2002, 2003 by lsi logic corporation. all rights reserved. ma[21:0] i/o ma[7] 1 = report device as not pci-x compatible 0 = report device as pci-x compatible ma[6] 1 = pcifunction1 subsyscntlid lsb will be a ? 0 = pcifunction1 subsyscntlid lsb will be a ? ma[5] 1 = pcifunction0 subsyscntlid lsb will be a ? 0 = pcifunction0 subsyscntlid lsb will be a ? ma[4] 1 = pcifunction1 deviceid lsb will be a ? 0 = pcifunction1 deviceid lsb will be a ? ma[3] 1 = pcifunction0 deviceid lsb will be a ? 0 = pcifunction0 deviceid lsb will be a ? ma[2] 1 = force single function device (eeprom override) 0 = do not force single function device (eeprom override) ma[1] not applicable for power-on sense ma[0] 1 = set to this if eeprom size is 1 kbyte, 2 kbytes, 4 kbytes, 8 kbytes, or 16 kbytes 0 = set to this if eeprom size is 32 kbytes or 64 kbytes moe[1:0]/ o f26, e26 3.3 v bidir 8ma memory output enable . when asserted low, the selected sram or flash (moe[1]/) device may drive data. this signal is typically an asynchronous input to sram and/or flash devices. the two output enables allow for interleaving con?urations, with moe[0]/ being the only output enable used for a noninterleaved implementation. mwe[1:0]/ o f25, g23 3.3 v bidir 4ma memory write enables . these active-low bank write enables are required for interleaving con?urations. mwe[0]/ is the only write enable used for a noninterleaved implementation. flashcs/ o e24 3.3 v bidir 4ma flash chip select . this active-low chip select allows connection of a single, 8-bit flash rom device. table 4.3 memory interface (cont.) signal i/o bga pad no. pad type description
memory interface 4-13 copyright 2002, 2003 by lsi logic corporation. all rights reserved. mclk b j26 3.3 v 8 ma t/s output memory clock . all synchronous ram control/data signals are referenced to the rising edge of this clock. exceptions are moe/ and zz, which are typically asynchronous inputs to sram and/or flash devices. adsc/ b j25 3.3 v 4 ma t/s output address-strobe-controller . initiates read, write, or chip deselect cycle. when this signal is asserted, it also latches the memory address signals. adv/ b h26 3.3 v 4 ma t/s output advance . when asserted low, the adv/ input causes a selected synchronous sram to increment its burst address counter. bwe[3:0]/ o h25, h23, g26, g25 3.3 v bidir 4ma memory byte write enables . these active-low, byte lane write enables allow writing of partial words to memory. ramcs/ o f24 3.3 v bidir 4ma ram chip select . this pin is an active-low synchronous chip select for all ssrams (up to four ssrams for interleaved and depth expanded con?uration without additional decode logic). zz o f23 3.3 v bidir 4ma snooze control . asserting this output high causes a synchronous sram to enter its lowest power state (not all rams support this function). table 4.3 memory interface (cont.) signal i/o bga pad no. pad type description
4-14 signal descriptions copyright 2002, 2003 by lsi logic corporation. all rights reserved. 4.4 con?uration and miscellaneous table 4.4 shows the con?uration and miscellaneous signals. table 4.4 con?uration and miscellaneous signal i/o bga pad no. pad type description gpio[5:0] i/o j2, k3, h2, k1, j3, j1 3.3 v bidir 8 ma with pull-up general purpose i/o pins. these pins default to input mode on reset. these signals are controlled/observed by firmware and may be configured as inputs or outputs. gpio[3] may be optionally enabled as an external interrupt source to the arm risc processor core. refer also to the gpio[2] pin description in ta b l e 4 . 1 on page 4-3 for details on other operational capabilities of this signal. led[4:0]/ o b3, e7, d6, b4, d7 3.3 v bidir 8ma led outputs . these output signals may be controlled by firmware or driven by chip activity. when configured as activity driven, the led[n] outputs have the following meanings when asserted low: led[4]: channel 1 fault led[3]: channel 1 active led[2]: channel 0 fault led[1]: channel 0 active led[0]: firmware controlled (heartbeat) scl o b21 3.3 v 4ma bidir with pull-up serial eeprom clock . sda i/o a21 3.3 v 4ma bidir with pull-up serial eeprom data . mode[7:0] i a4, c3, a5, d4, b2, e1, c2, e3 3.3 v ttl input with pull-up mode select. this 8-bit bus de?es operational and test modes for the chip. valid mode encodings are as follows: mode[7:0] = 00111111 interleaved pbsram mode[7:0] = 00011111 noninterleaved pbsram bzrset p3 reference resistor node for the pci-x impedance controller. bzvdd r4 reference resistor node for the pci-x impedance controller.
test and i/o processor debug 4-15 copyright 2002, 2003 by lsi logic corporation. all rights reserved. 4.5 test and i/o processor debug table 4.5 shows the test and i/o processor debug signals. table 4.5 test and i/o processor debug signal i/o bga pad no. pad type description tck i l2 3.3 v schmitt with pull-up jtag/ctxmgr debug test clock . trst/ i m2 3.3 v schmitt with pull-up jtag/debug test reset . asynchronous active low. tdi i n4 3.3 v schmitt with pull-up jtag/ctxmgr debug test data in . tdo b m4 3.3 v 4 ma t/s output with pull-up jtag/ctxmgr debug test data out . tms_chip i l4 3.3 v schmitt with pull-up jtag test mode select . tms_ice i n1 3.3 v schmitt with pull-up ctxmgr debug test mode select . test[9] o n3 factory test pin . not used during normal operation, and must be left unconnected. test[8:0] i c6, h5, f3, f1, n2, l1, e8, b5, a6 factory test pins . not used during normal operation, and must be tied to vddio (3.3 v) or vssio (0 v) depending on pin, as follows: test[8] 3.3 v test[7] 3.3 v test[6] 3.3 v test[5] 3.3 v test[4] 0 v test[3] 0 v test[2] 0 v test[1] 0 v test[0] 0 v
4-16 signal descriptions copyright 2002, 2003 by lsi logic corporation. all rights reserved. 4.6 power and ground table 4.6 shows the power and ground signals. table 4.6 power and ground signal bga pad no. description voltage vddc 1 c9, c18, d5, d22, e15, g5, g22, j4, j23, m5, m22, r5, t22, w22, aa1, ab4, ab7, ab11, ab16, ab20, ab23, ac9, ac18 core power. 1.8 v vssc c5, c10, c17, c22, e4, e12, e23, h4, h22, l5, l22, p26, t5, v4, v23, y5, y22, ab8, ab12, ab15, ab19, ac5, ac22 core ground. 0 v vddio a2, a26, b1, c7, c11, c15, c19, c23, d3, e6, e10, e14, e18, e22, e25, f5, g24, h3, j22, k5, l24, m3, n22, p5, r24, t3, u22, v5, w24, y3, aa22, ab3, ab5, ab9, ab13, ab17, ab21, ac24, ad5, ad8, ad12, ad16, ad20, ae26, af1, af25 i/o power. 3.3 v vssio a1, a25, b26, c4, c8, c12, c16, c20, d24, e2, e5, e9, e13, e17, e21, f22, g3, h24, j5, k22, l3, l11, l12, l13, l14, l15, l16, m11, m12, m13, m14, m15, m16, m24, n5, n11, n12, n13, n14, n15, n16, p11, p12, p13, p14, p15, p16, p22, r3, r11, r12, r13, r14, r15, r16, t11, t12, t13, t14, t15, t16, t24, u5, v22, w3, y24, aa5, ab6, ab10, ab14, ab18, ab22, ab25, ac4, ad7, ad11, ad15, ad19, ad23, ae1, af2, af26 i/o ground. 0 v
power and ground 4-17 copyright 2002, 2003 by lsi logic corporation. all rights reserved. v5pcix u1, u2, ac2, ac7, ac16, ac23, ad1, ae2, af9, af11, af12, af17, af24 pci-x 5 v reference power supply. 5 v refpllvdd d2 analog power for pci fsn cell. 1.8 v refpllvss g4 analog ground for pci fsn cell. 0 v pcipllvdd ad3 analog power for arm clock generation. 1.8 v pcipllvss ad4 analog ground for arm clock generation. 0 v rxbvdd0 b13 analog power for integrated transceiver core. 1.8 v rxbvss0 a13 analog ground for integrated transceiver core. 0 v rxbvdd1 d16 analog power for integrated transceiver core. 1.8 v rxbvss1 d17 analog ground for integrated transceiver core. 0 v rxvdd0 d13 analog power for integrated transceiver core. 1.8 v rxvss0 d12 analog ground for integrated transceiver core. 0 v rxvdd1 a18 analog power for integrated transceiver core. 1.8 v rxvss1 b18 analog ground for integrated transceiver core. 0 v txbvdd0 d11 analog power for integrated transceiver core. 1.8 v txbvss0 d10 analog ground for integrated transceiver core. 0 v txbvdd1 b14 analog power for integrated transceiver core. 1.8 v txbvss1 a14 analog ground for integrated transceiver core. 0 v txvdd0 a9 analog power for integrated transceiver core. 1.8 v txvss0 b9 analog ground for integrated transceiver core. 0 v txvdd1 d14 analog power for integrated transceiver core. 1.8 v txvss1 d15 analog ground for integrated transceiver core. 0 v 1. the required core voltage on the LSIFC929X is 1.8 v. the i/o pads are 5 v tolerant. the pci i/o voltage requires 3.3 v, and the gigablaze fibre channel transceiver interface requires 1.8 v. con?ure the power supply to the chip so that the lower voltages power-up in advance of the higher voltages. the recommended power sequencing depends on the number of supplies used. for a pci system with pci buffers, the recommended power sequence is 1.8 v, then 5 v, and then 3.3 v; or make certain that the following conditions are met during the power cycling: (vdd1.8 > 1 v) before (vdd3.3 > 1 v) vdd5 > (vdd3.3 -0.3 v) table 4.6 power and ground (cont.) signal bga pad no. description voltage
4-18 signal descriptions copyright 2002, 2003 by lsi logic corporation. all rights reserved.
LSIFC929X dual channel fibre channel i/o processor technical manual 5-1 copyright 2002, 2003 by lsi logic corporation. all rights reserved. chapter 5 pci-x functional description this chapter provides a general description of the pci-x features contained in the LSIFC929X dual channel fibre channel i/o processor chip. the chapter contains the following sections: ? section 5.1, ?verview ? section 5.2, ?ci-x addressing ? section 5.3, ?ci/pci-x bus commands and implementation ? section 5.4, ?ci arbitration ? section 5.5, ?ci cache mode 5.1 overview the host pci-x interface complies with the pci local bus speci?ation, revision 2.2, and the pci-x addendum to the pci local bus speci?ation, revision 1.0a . the LSIFC929X supports up to a 133 mhz, 64-bit pci-x bus. the LSIFC929X supports 64-bit addressing with dual address cycle (dac). the LSIFC929X is a true multifunction pci-x device that presents a single electrical load to the pci-x bus. the LSIFC929X uses a single req/-gnt/ pair to arbitrate for pci-x bus mastership. separate interrupt signals for pci function [0] and pci function [1] allow independent control of the two pci functions.
5-2 pci-x functional description copyright 2002, 2003 by lsi logic corporation. all rights reserved. 5.2 pci-x addressing the three physical address spaces the pci speci?ation de?es are: ? pci con?uration space ? pci i/o space for operating registers ? pci memory space for operating registers the following sections describe the pci address spaces. 5.2.1 pci con?uration space the LSIFC929X de?es an independent set of pci con?uration space registers for each pci function. each con?uration space is a contiguous, 256-x-8-bit set of addresses. the system bios initializes the con?uration registers using pci-x con?uration cycles. the LSIFC929X decodes the c_be[3:0]/ ?ld to determine whether a pci-x cycle intends to access the con?uration register space. the idsel signal behaves as a chip select signal that enables access to the con?uration register space only. the LSIFC929X ignores con?uration read/write cycles when idsel is not asserted. because the LSIFC929X is a multifunction pci-x device, bits ad[10:8] decode either the pci function [0] con?uration space (ad[10:8] = 0b000) or the pci function [1] con?uration space (ad[10:8] = 0b001). the LSIFC929X does not respond to any other encodings of ad[10:8]. bits ad[7:2] select one of the 64 dword registers in the LSIFC929X pci con?uration space. bits ad[1:0] determine whether the con?uration command is a type 0 con?uration command (ad[1:0] = 0b00) or a type 1 con?uration command (ad[1:0] = 0b01). because the LSIFC929X is not a pci bridge device, all pci con?uration commands designated for the LSIFC929X must be type 0. bits c_be[3:0]/ address the individual bytes within each dword and determine the type of access to perform.
pci/pci-x bus commands and implementation 5-3 copyright 2002, 2003 by lsi logic corporation. all rights reserved. 5.2.2 pci i/o space the pci speci?ation de?es i/o space as a contiguous 32-bit, i/o address that all system resources share, including the LSIFC929X. the i/o base address register determines the 256-byte pci i/o area that the pci device occupies. 5.2.3 pci memory space the LSIFC929X contains two pci memory spaces: pci memory space [0] and pci memory space [1]. pci memory space [0] supports normal memory accesses, while pci memory space [1] supports diagnostic memory accesses. the LSIFC929X requires 64 kbytes of memory space. the pci speci?ation de?es memory space as a contiguous, 64-bit memory address that all system resources share. the memory [0] base address low and memory [0] base address high registers determine which 64 kbyte memory area pci memory space [0] occupies. the memory [1] base address low and memory [1] base address high registers determine which 64 kbyte memory area pci memory space [1] occupies. 5.3 pci/pci-x bus commands and implementation bus commands indicate to the target the type of transaction the master is requesting. the master encodes the bus commands on the c_be[3:0]/ lines during the address phase. the pci/pci-x bus commands and their encodings appear in table 5.1 .
5-4 pci-x functional description copyright 2002, 2003 by lsi logic corporation. all rights reserved. the following sections describe how the LSIFC929X implements these commands. table 5.1 pci/pci-x bus commands and encodings 1 1. the LSIFC929X ignores reserved commands as a slave and never generates them as a master. c_be[3:0]/ pci bus command pci-x bus command supports as master supports as slave 0b0000 interrupt acknowledge interrupt acknowledge no no 0b0001 special cycle special cycle no no 0b0010 i/o read i/o read yes yes 0b0011 i/o write i/o write yes yes 0b0100 reserved reserved n/a n/a 0b0101 reserved reserved n/a n/a 0b0110 memory read memory read dword yes yes 0b0111 memory write memory write yes yes 0b1000 reserved alias to memory read block pci: n/a pci-x: no pci: n/a pci-x: yes 0b1001 reserved alias to memory write block pci: n/a pci-x: no pci: n/a pci-x: yes 0b1010 con?uration read con?uration read no yes 0b1011 con?uration write con?uration write no yes 0b1100 memory read multiple split completion yes yes 2 2. when acting as a slave in the pci mode, the LSIFC929X supports this command as the pci memory read command. 0b1101 dual address cycles (dac) dual address cycles (dac) ye s ye s 0b1110 memory read line memory read block yes yes 2 0b1111 memory write and invalidate memory write block yes yes 3 3. when acting as a slave in the pci mode, the LSIFC929X supports this command as the pci memory write command.
pci/pci-x bus commands and implementation 5-5 copyright 2002, 2003 by lsi logic corporation. all rights reserved. 5.3.1 interrupt acknowledge command the LSIFC929X ignores this command as a slave and never generates it as a master. 5.3.2 special cycle command the LSIFC929X ignores this command as a slave and never generates it as a master. 5.3.3 i/o read command the i/o read command reads data from an agent mapped in the i/o address space. when decoding i/o commands, the LSIFC929X decodes the lower 32 address bits and ignores the upper 32 address bits. the LSIFC929X supports this command when operating in either the pci or pci-x bus mode. 5.3.4 i/o write command the i/o write command writes data to an agent mapped in the i/o address space. when decoding i/o commands, the LSIFC929X decodes the lower 32 address bits and ignores the upper 32 address bits. the LSIFC929X supports this command when operating in either the pci or pci-x bus mode. 5.3.5 memory read command the LSIFC929X uses the memory read command to read data from an agent mapped in the memory address space. the target can perform an anticipatory read if such a read produces no side effects. the LSIFC929X supports this command when operating in the pci bus mode. 5.3.6 memory read dword command the memory read dword command reads up to a single dword of data from an agent mapped in the memory address space and can only be initiated as a 32-bit transaction. the target can perform an anticipatory read if such a read produces no side effects. the LSIFC929X supports this command when operating in the pci-x bus mode.
5-6 pci-x functional description copyright 2002, 2003 by lsi logic corporation. all rights reserved. 5.3.7 memory write command the memory write command writes data to an agent mapped in the memory address space. the target assumes responsibility for data coherency when it returns ?eady? the LSIFC929X supports this command when operating in either the pci or pci-x bus mode. 5.3.8 alias to memory read block command this command is reserved for future implementations of the pci speci?ation. the LSIFC929X never generates this command as a master. when a slave, the LSIFC929X supports this command using the memory read block command. 5.3.9 alias to memory write block command this command is reserved for future implementations of the pci speci?ation. the LSIFC929X never generates this command as a master. when a slave, the LSIFC929X supports this command using the memory write block command. 5.3.10 con?uration read command the con?uration read command reads the con?uration space of a device. the LSIFC929X never generates this command as a master, but does respond to it as a slave. a device on the pci bus selects the LSIFC929X by asserting its idsel signal when bits ad[1:0] = 0b00. during the address phase of a con?uration cycle, bits ad[7:2] address one of the 64 dword registers in the con?uration space of each device. c_be[3:0]/ address the individual bytes within each dword register and determine the type of access to perform. bits ad[10:8] address either the pci function [0] con?uration space (ad[10:8] = 0b000) or the pci function [1] con?uration space (ad[10:8] = 0b001). the LSIFC929X treats ad[63:11] as logical don? cares. 5.3.11 con?uration write command the con?uration write command writes the con?uration space of a device. the LSIFC929X never generates this command as a master, but does respond to it as a slave. a device on the pci bus selects the LSIFC929X by asserting its idsel signal when bits ad[1:0] = 0b00.
pci/pci-x bus commands and implementation 5-7 copyright 2002, 2003 by lsi logic corporation. all rights reserved. during the address phase of a con?uration cycle, bits ad[7:2] address one of the 64 dword registers in the con?uration space of each device. c_be[3:0]/ address the individual bytes within each dword register and determine the type of access to perform. bits ad[10:8] decode either the pci function [0] con?uration space (ad[10:8] = 0b000) or the pci function [1] con?uration space (ad[10:8] = 0b001). the LSIFC929X treats ad[63:11] as logical don? cares. 5.3.12 memory read multiple command the memory read multiple command is identical to the memory read command, except it additionally indicates that the master intends to fetch multiple cache lines before disconnecting. the LSIFC929X supports pci memory read multiple functionality when operating in the pci mode and determines when to issue a memory read multiple command instead of a memory read command. burst size selection the memory read multiple command reads multiple cache lines of data during a single bus ownership. the number of cache lines the LSIFC929X reads is a multiple of the cache line size, which the pci local bus speci?ation, revision 2.2, provides. the LSIFC929X selects the largest multiple of the cache line size based on the amount of data to transfer. 5.3.13 split completion command split transactions in pci-x replace the delayed transactions in conventional pci. the LSIFC929X supports up to eight outstanding split transactions when operating in the pci-x mode. a split transaction consists of at least two separate bus transactions: a split request, which the requester initiates; and one or more split completion commands, which the completer initiates. the pci-x addendum to the pci local bus speci?ation, revision 1.0a, permits split transaction completion for the memory read block, alias to memory read block, memory read dword, interrupt acknowledge, i/o read, i/o write, con?uration read, and con?uration write commands. when operating in the pci-x mode, the LSIFC929X supports the split completion command for all of these commands except the interrupt acknowledge command, which the LSIFC929X neither responds to nor generates.
5-8 pci-x functional description copyright 2002, 2003 by lsi logic corporation. all rights reserved. 5.3.14 dual address cycles (dac) command the LSIFC929X performs dual address cycles (dac), according to the pci local bus speci?ation, revision 2.2 . the LSIFC929X supports this command when operating in either the pci or pci-x bus mode. 5.3.15 memory read line command this command is identical to the memory read command except it additionally indicates that the master intends to fetch a complete cache line. the LSIFC929X supports this command when operating in the pci mode. 5.3.16 memory read block command the LSIFC929X uses this command to read from memory. the LSIFC929X supports this command when operating in the pci-x mode. 5.3.17 memory write and invalidate command the memory write and invalidate command is identical to the memory write command, except it additionally guarantees a minimum transfer of one complete cache line. the master uses this command when it intends to write all bytes within the addressed cache line in a single pci transaction unless interrupted by the target. this command requires implementation of the pci cache line size register. the LSIFC929X determines when to issue a write and invalidate command instead of a memory write command, and supports this command when operating in the pci bus mode. 5.3.17.1 alignment the LSIFC929X uses the calculated line size value to determine whether the current address aligns to the cache line size. if the address does not align, the LSIFC929X bursts data using a noncache command. if the starting address aligns, the LSIFC929X issues a memory write and invalidate command using the cache line size as the burst size.
pci arbitration 5-9 copyright 2002, 2003 by lsi logic corporation. all rights reserved. 5.3.17.2 multiple cache line transfers the memory write and invalidate command can write multiple cache lines of data in a single bus ownership. the LSIFC929X issues a burst transfer as soon as it reaches a cache line boundary. the pci local bus speci?ation states that the transfer size must be a multiple of the cache line size. the LSIFC929X selects the largest multiple of the cache line size based on the transfer size. when the dma buffer contains less data than the value cache line size register speci?s, the LSIFC929X issues a memory write command on the next cache boundary to complete the data transfer. 5.3.18 memory write block command the LSIFC929X uses this command to burst data to memory. the LSIFC929X supports this command when operating in the pci-x bus mode. 5.4 pci arbitration the LSIFC929X contains independent bus mastering functions for each of the scsi functions and for the system interface. the system interface bus mastering function manages dma operations as well as the request and reply message frames. the scsi channel bus mastering functions manage data transfers across the scsi channels. the LSIFC929X uses a single req/-gnt/ signal pair to arbitrate for access to the pci bus. to ensure fair access to the pci bus, the internal arbiter uses a round robin arbitration scheme to decide which of the three internal bus mastering functions can arbitrate for access to the pci bus. 5.5 pci cache mode the LSIFC929X supports an 8-bit, cache line size register. this register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. the LSIFC929X determines when to issue a pci cache command (memory read line, memory read multiple, and memory write and invalidate) or pci noncache command (memory read or memory write).
5-10 pci-x functional description copyright 2002, 2003 by lsi logic corporation. all rights reserved.
LSIFC929X dual channel fibre channel i/o processor technical manual 6-1 copyright 2002, 2003 by lsi logic corporation. all rights reserved. chapter 6 registers this chapter describes the pci host register space. the chapter consists of the following sections: ? section 6.1, ?ci-x con?uration space register description ? section 6.2, ?ci i/o space and memory space register description ? section 6.3, ?hared memory the register map at the beginning of each register description provides the default bit settings for the register. shading indicates a reserved bit or register. do not access the reserved address areas. there are two pci functions on the LSIFC929X. each pci function has its own independent interrupt pin and its own pci address space. the pci system address space consists of three regions: pci con?uration space, pci memory space, and pci i/o space. pci con?uration space supports the identi?ation, con?uration, initialization, and error management functions for the LSIFC929X pci devices. pci memory space [0] and pci memory space [1] form pci memory space. pci memory space [1] provides diagnostic memory accesses. pci i/o space and pci memory space [0] provide normal system access to memory.
6-2 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. 6.1 pci-x con?uration space register description this section provides bit level descriptions of the pci con?uration space registers. table 6.1 de?es the pci con?uration space registers. a separate set of pci con?uration space registers exists for each pci function. the LSIFC929X enables, orders, and locates the pci-extended capability register structures (power management, messaged signaled interrupts, and pci-x) to optimize device performance. the LSIFC929X does not hardcode the location and order of the pci-extended capability structures. the address and location of the pci-extended capability structures are subject to change. to access a pci-extended capability structure, follow the pointers held in the capability pointer registers and identify the extended capability structure with the capability id register for the given structure.
pci-x con?uration space register description 6-3 copyright 2002, 2003 by lsi logic corporation. all rights reserved. table 6.1 LSIFC929X pci-x con?uration space address map 31 16 15 0 offset page device id vendor id 0x00 6-4 status command 0x04 6-5 class code revision id 0x08 6-9 reserved header type latency timer cache line size 0x0c 6-10 i/o base address 0x10 6-12 memory [0] base address low 0x14 6-12 memory [0] base address high 0x18 6-13 memory [1] base address low 0x1c 6-13 memory [1] base address high 0x20 6-14 reserved 0x24 0x28 subsystem id subsystem vendor id 0x2c 6-15 expansion rom base address 0x30 6-16 reserved capabilities pointer 0x34 6-17 0x38 maximum latency minimum grant interrupt pin interrupt line 0x3c 6-18 reserved 0x40 0x7f power management capabilities pm next pointer pm capability id 6-20 pm data pm bse power management control/status 6-22 reserved message control msi next pointer msi capability id 6-24 message address 6-26 message upper address 6-26 message data 6-27 reserved pci-x command pci-x next pointer pci-x capability id 6-28 pci-x status 6-30 reserved
6-4 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x00?x01 vendor id read only vendor id [15:0] this 16-bit register identi?s the device manufacturer. the vendor id is 0x1000. register: 0x02?x03 device id read only device id [15:0] this register identi?s the particular device. the most signi?ant 12 bits are hardcoded to a constant of 0x062. the lsb is dependent upon the power-on-sense functions corresponding to the states of pins ma[4] and ma[3] as decoded in table 6.2 . 15 8 7 0 vendor id 0001000000000000 15 8 7 0 device id 000001100010001x
pci-x con?uration space register description 6-5 copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x04?x05 command read/write this register provides coarse control over how the pci function generates and responds to pci cycles. writing a zero to this register logically disconnects the LSIFC929X pci function from the pci bus for all accesses except con?uration accesses. reserved [15:9] this ?ld is reserved. serr/ enable 8 setting this bit enables the LSIFC929X to activate the serr/ driver. clearing this bit disables the serr/ driver. reserved 7 this bit is reserved. table 6.2 device id values single/dual channel state of ma[4:3] device id function 1 dual channel ma[4] = 0 0x0626 dual channel ma[4] = 1 0x0627 single channel ma[4] = 0 0x0628 single channel ma[4] = 1 0x0629 function 0 dual channel ma[3] = 0 0x0626 dual channel ma[3] = 1 0x0627 single channel ma[3] = 0 0x0628 single channel ma[3] = 1 0x0629 15 8 7 0 command 0 0 0 0 0 0 00 00 00 0000
6-6 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. enable parity error response 6 setting this bit enables the LSIFC929X pci function to detect parity errors on the pci bus and report these errors to the system. clearing this bit causes the LSIFC929X pci function to set the detected parity error bit (bit 15 in the status register (register 0x06?x07)) but not assert the perr/ signal when the pci function detects a parity error. this bit only affects parity checking. the pci function always generates parity for the pci bus. reserved 5 this bit is reserved. write and invalidate enable 4 setting this bit enables the pci function to generate write and invalidate commands on the pci bus when operating in the conventional pci mode. reserved 3 this bit is reserved. enable bus mastering 2 setting this bit allows the pci function to behave as a pci bus master. clearing this bit disables the pci function from generating pci bus master accesses. enable memory space 1 this bit controls the ability of the pci function to respond to memory space accesses. setting this bit allows the LSIFC929X to respond to memory space accesses at the address range speci?d by the memory [0] base address low , memory [0] base address high , memory [1] base address low , memory [1] base address high , and the expansion rom base address registers. clearing this bit disables the pci function response to memory space accesses. enable i/o space 0 this bit controls the LSIFC929X pci function response to i/o space accesses. setting this bit enables the pci function to respond to i/o space accesses at the address range the pci con?uration space i/o base address register speci?s. clearing this bit disables the pci function response to i/o space accesses.
pci-x con?uration space register description 6-7 copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x06?x07 status read/write reads to this register behave normally. to clear a bit location that is currently set, write the bit to one (1). for example, to clear bit 15 when it is set, and not affect any other bits, write 0x8000 to the register. detected parity error (from slave) 15 this bit is set according to the pci local bus speci?ation, revision 2.2 , and the pci-x addendum to the pci local bus speci?ation, revision 1.0a . signaled system error 14 the LSIFC929X pci function sets this bit when asserting the serr/ signal. received master abort (from master) 13 a master device sets this bit when a master abort command terminates its transaction (except for special cycle). received target abort (from master) 12 a master device sets this bit when a target abort command terminates its transaction. reserved 11 this bit is reserved. devsel/ timing [10:9] these two read-only bits encode the timing of the devsel/ signal and indicate the slowest time that a device asserts the devsel/ signal for any bus command except con?uration read and con?uration write. the LSIFC929X only supports medium devsel/ timing. the possible timing values are as follows: 15 8 7 0 status 0000 0010 0 011 0 0 0 0
6-8 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. data parity error reported 8 this bit is set according to the pci local bus speci?ation, revision 2.2 , and the pci-x addendum to the pci local bus speci?ation, revision 1.0a . refer to bit 0 of the pci-x command register for details. reserved [7:6] this ?ld is reserved. 66 mhz capable 5 the ma[10] power-on sense pin controls this bit. allowing the internal pull-down to pull ma[10] low sets this bit and indicates to the host system that the LSIFC929X pci function is capable of operating at 66 mhz. pulling ma[10] high clears this bit and indicates to the host system that the LSIFC929X pci function is not capable of operating at 66 mhz. refer to table 4.3 on page 4-10 for details. new capabilities 4 the LSIFC929X pci function sets this read-only bit to indicate a list of pci extended capabilities such as pci power management, message signaled interrupt (msi), and pci-x support. reserved [3:0] this ?ld is reserved. 0b00 fast 0b01 medium 0b10 slow 0b11 reserved
pci-x con?uration space register description 6-9 copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x08 revision id read/write revision id [7:0] this register indicates the current revision level of the device. register: 0x09?x0b class code read only class code [23:0] this 24-bit register identi?s the generic function of this device. the upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identi?s a speci? register-level programming interface. the value of this register is 0x0c0400, and is written by the seeprom (provided the seeprom is present in the system). if no seeprom is present in the system, the default class code is 0x010000. 7 0 revision id xxxxxxxx 23 16 15 8 7 0 class code 000000010000000000000000
6-10 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x0c cache line size read/write cache line size [7:3] this register speci?s the system cache line size in units of 32-bit words. in the conventional pci mode, the LSIFC929X pci function uses this register to determine whether to use write and invalidate or write commands for performing write cycles. programming this register to a number other than a nonzero power of two disables the the use of the pci performance commands to execute data transfers. the LSIFC929X pci function ignores this register when operating in the pci-x mode. reserved [2:0] this ?ld is reserved. register: 0x0d latency timer read/write latency timer [7:4] this register speci?s, in units of pci bus clocks, the value of the latency timer for this pci bus master. reserved [3:0] this ?ld is reserved. 7 0 cache line size 00000 0 0 0 7 0 latency timer 0x00 0 0 0 0
pci-x con?uration space register description 6-11 copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x0e header type read only header type [7:0] this 8-bit register identi?s the layout of bytes 0x10 through 0x3f in con?uration space and also indicates whether this device is a single function or multifunction pci device. register: 0x0f reserved reserved [7:0] this register is reserved. 7 0 header type x0000000 7 0 reserved 0 0 0 0 0 0 0 0
6-12 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x10?x13 i/o base address read/write this register maps the operating register set into i/o space. the LSIFC929X requires 256 bytes of i/o space for this register. hardware sets bit 0 to 0b1. bit 1 is reserved and returns 0b0 on all reads. i/o base address [31:2] this ?ld contains the i/o base address. reserved [1:0] this ?ld is reserved. register: 0x14?x17 memory [0] base address low read/write the memory [0] base address low register and the memory [0] base address high register map scsi operating registers into memory space [0]. the memory [0] base address low register contains the lower 32 bits of the memory space [0] base address. hardware programs bits [9:0] to 0b0000000100, which indicates that the memory space [0] base address is 64 bits wide and that the memory data is not prefetchable. the LSIFC929X requires 1024 bytes of memory space. memory [0] base address low [31:0] this ?ld contains the memory [0] base address low address. 31 24 23 16 15 8 7 0 i/o base address 000000000000000000000000 0 0 0 0 0 0 0 1 31 24 23 16 15 8 7 0 memory [0] base address low 000000000000000000000 0 0 0 0 0 0 0 0 1 0 0
pci-x con?uration space register description 6-13 copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x18?x1b memory [0] base address high read/write the memory [0] base address high register and the memory [0] base address low register map scsi operating registers into memory space [0]. the memory [0] base address high register contains the upper 32 bits of the memory space [0] base address. the LSIFC929X requires 1024 bytes of memory space. memory [0] base address high [31:0] this ?ld contains the memory [0] base address high address. register: 0x1c?x1f memory [1] base address low read/write the memory [1] base address low register and the memory [1] base address high register map the ram into memory space [1]. the memory [1] base address low register contains the lower 32 bits of the memory space [1] base address. hardware programs bits [12:0] to 0b0000000000100, which indicates that the memory space [1] base address is 64 bits wide and that the memory data is not prefetchable. the LSIFC929X requires 64 kbytes of memory for memory space [1]. memory [1] base address low [31:0] this ?ld contains the memory [1] base address low address. 31 24 23 16 15 8 7 0 memory [0] base address high 00000000000000000000000000000000 31 24 23 16 15 8 7 0 memory [1] base address low 000000000000000000 0 0 0 0 0 0 0 0 0 0 0 1 0 0
6-14 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x20?x23 memory [1] base address high read/write the memory [1] base address low register and the memory [1] base address high register map the ram into memory space [1]. the memory [1] base address low register contains the upper 32 bits of the memory space [1] base address. the LSIFC929X requires 64 kbytes of memory for memory space [1]. memory [1] base address high [31:0] this ?ld contains the memory [1] base address high address. register: 0x24?x27 reserved reserved [31:0] this register is reserved. register: 0x28?x2b reserved reserved [31:0] this register is reserved. 31 24 23 16 15 8 7 0 memory [1] base address high 00000000000000000000000000000000 31 24 23 16 15 8 7 0 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 24 23 16 15 8 7 0 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
pci-x con?uration space register description 6-15 copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x2c?x2d subsystem vendor id read only svid subsystem vendor id [15:0] this 16-bit register uniquely identi?s the vendor that manufactures the add-in board or subsystem where the LSIFC929X resides. this register provides a mechanism for an add-in card vendor to distinguish their cards from those of another vendor, even if the cards use the same pci controller (and have the same vendor id and device id). the external serial eeprom can hold a vendor-speci?, 16-bit value for this register, which the board designer must obtain from the pci special interest group (pci-sig). register: 0x2e?x2f subsystem id read only sid subsystem id [15:0] this 16-bit register uniquely identifies the add-in board or subsystem where this pci device resides. this register provides a mechanism for an add-in card vendor to distinguish their cards from one another even if the cards use the same pci controller (and have the same vendor id and device id). the board designer can store a vendor-specific, 16-bit value in an external serial eeprom. 15 8 7 0 subsystem vendor id xxxxxxxxxxxxxxxx 15 8 7 0 subsystem id xxxxxxxxxxxxxxxx
6-16 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x30?x33 expansion rom base address read/write this 32-bit register contains the base address and size information for the expansion rom. expansion rom base address [31:11] these bits correspond to the upper 21 bits of the expansion rom base address. the host system detects the size of the external memory by ?st writing 0xffffffff to this register and then reading the register back. the LSIFC929X responds with zeros in all don? care locations. the least signi?ant one (1) that remains represents the binary version of the external memory size. for example, to indicate an external memory size of 32 kbytes, this register returns ones in the upper 17 bits when written with 0xffffffff and read back. reserved [10:1] this ?ld is reserved. expansion rom enable 0 this bit controls whether the device accepts accesses to its expansion rom. setting this bit enables address decoding. depending on the system con?uration, the device can optionally use an expansion rom. note that to access the expansion rom, the user must also set bit 1 in the pci command register. 31 24 23 16 15 8 7 0 expansion rom base address 000000000000000000000 0 0 0 0 0 0 0 0 0 00
pci-x con?uration space register description 6-17 copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x34 capabilities pointer read only capabilities pointer [7:0] this register indicates the location of the ?st extended capabilities register in pci con?uration space. the value of this register varies according to system con?uration. register: 0x35?x37 reserved reserved [23:0] this register is reserved. register: 0x38?x3b reserved reserved [31:0] this register is reserved. 7 0 capabilities pointer xxxxxxxx 23 16 15 8 7 0 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 24 23 16 15 8 7 0 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6-18 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x3c interrupt line read/write interrupt line [7:0] this register communicates interrupt line routing information. power-on-self-test (post) software writes the routing information into this register as it con?ures the system. this register indicates the system interrupt controller input to which this pci function interrupt pin connects. system architecture determines the values in this register. register: 0x3d interrupt pin read only interrupt pin [7:0] the encoding of this read-only register is unique to each function on the LSIFC929X. it indicates which interrupt pin the function uses. the value for function [0] is 0x01, which indicates that function [0] presents interrupts on the inta/ or alt_inta pins. the value for function [1] is 0x02, which indicates that function [1] presents interrupts on the intb/ or alt_intb/ pins. 7 0 interrupt line 00000000 7 0 function [0] interrupt pin 00000001 function [1] interrupt pin 00000010
pci-x con?uration space register description 6-19 copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x3e minimum grant read only min_gnt [7:0] this register speci?s the desired settings for latency timer values in units of 0.25 s. the min_gnt ?ld speci?s how long of a burst period the device needs. the LSIFC929X sets this register to 0x10, indicating a burst period of 4.0 s. register: 0x3f maximum latency read only max_lat [7:0] this register speci?s the desired settings for latency timer values in units of 0.25 s. the max_lat ?ld speci?s how often the device needs to gain access to the pci bus. the LSIFC929X sets this register to 0x06, indicating a burst period of 1.5 s. 7 0 min_gnt 00010000 7 0 max_lat 00000110
6-20 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0xxx power management capability id read only power management capability id [7:0] this register indicates the type of the current data structure. it is set to 0x01 to indicate the power management data structure. register: 0xxx power management next pointer read only power management next pointer [7:0] this register contains the pointer to the next item in the pci function extended capabilities list. the value of this register varies according to system con?uration. 7 0 power management capability id 00000001 7 0 power management next pointer xxxxxxxx
pci-x con?uration space register description 6-21 copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0xxx power management capabilities read only pme_support [15:11] these bits de?e the power management states in which the device asserts the power management event (pme) pin. the LSIFC929X clears these bits because the LSIFC929X does not provide a pme signal. d2_support 10 the pci function sets this bit since the LSIFC929X supports power management state d2. d1_support 9 the pci function sets this bit because the LSIFC929X supports power management state d1. aux_current [8:6] the pci function clears this ?ld because the LSIFC929X does not support aux_current. device speci? initialization 5 the pci function clears this bit because it requires no special initialization before a generic class device driver can use it. reserved 4 this bit is reserved. pme clock 3 the LSIFC929X clears this bit because the chip does not provide a pme pin. version [2:0] the pci function programs these bits to 0b010 to indicate that the LSIFC929X complies with the pci power management interface speci?ation, revision 1.1 . 15 8 7 0 power management capabilities 0 0 0 0 0 110000 00010
6-22 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0xxx power management control/status read/write pme_status 15 the pci function clears this bit because the LSIFC929X does not support pme signal generation from d3 cold . data_scale [14:13] the pci function clears this bit because the LSIFC929X does not support the power management data register. data_select [12:9] the pci function clears these bits because the LSIFC929X does not support the power management data register. pme_enable 8 the pci function clears this bit because the LSIFC929X does not provide a pme signal and disables pme assertion. reserved [7:2] this ?ld is reserved. power state [1:0] these bits determine the current power state of the LSIFC929X. power states are as follows: 15 8 7 0 power management control/status 00000000 0 0 0 0 0 000 0b00 d0 0b01 d1 0b10 d2 0b11 d3 hot
pci-x con?uration space register description 6-23 copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0xxx power management bridge support extensions read only power management bridge support extensions [7:0] this register indicates pci bridge speci? functionality. the LSIFC929X always returns 0x00 in this register. register: 0xxx power management data read only power management data [7:0] this register provides an optional mechanism for the pci function to report state-dependent operating data. the LSIFC929X always returns 0x00 in this register. register: 0xxx msi capability id read only msi capability id [7:0] this register indicates the type of the current data structure. this register always returns 0x05, indicating a message signaled interrupt (msi). 7 0 power management bridge support extensions 00000000 7 0 power management data 00000000 7 0 msi capability id 00000101
6-24 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0xxx msi next pointer read only msi next pointer [7:0] this register points to the next item in the pci function extended capabilities list. the value of this register varies according to system con?uration. register: 0xxx message control read/write reserved [15:8] this ?ld is reserved. 64-bit address capable 7 the pci function sets this read-only bit to indicate support of a 64-bit message address. multiple message enable [6:4] these read/write bits indicate the number of messages that the host allocates to the LSIFC929X. the host system software allocates all or a subset of the requested messages by writing to this ?ld. the number of allocated request messages must align to a power of two. table 6.3 provides the bit encoding of this ?ld. 7 0 msi next pointer xxxxxxxx 15 8 7 0 message control 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
pci-x con?uration space register description 6-25 copyright 2002, 2003 by lsi logic corporation. all rights reserved. multiple message capable [3:1] these read-only bits indicate the number of messages that the LSIFC929X requests from the host. the host system software reads this ?ld to determine the number of requested messages. the number of requested messages must align to a power of two. the LSIFC929X sets this ?ld to 0b000 to request one message. all other encodings of this ?ld are reserved. msi enable 0 system software sets this bit to enable msi. setting this bit enables the device to use msi to interrupt the host and request service. table 6.3 multiple message enable field bit encoding bits [6:4] encoding number of allocated messages 0b000 1 0b001 2 0b010 4 0b011 8 0b100 16 0b101 32 0b110 reserved 0b111 reserved
6-26 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0xxx message address read/write message address [31:2] this ?ld contains message address bits [31:2] for the msi memory write transaction. the host system speci?s and aligns the message address to a dword. during the address phase, the LSIFC929X drives message address[1:0] to 0b00. reserved [1:0] this ?ld is reserved. register: 0xxx message upper address read/write message upper address [31:0] the LSIFC929X supports 64-bit msi. this register contains the upper 32 bits of the 64-bit message address, which the system speci?s. the host system software can program this register to 0x0000 to force the pci function to generate 32-bit message addresses. 31 24 23 16 15 8 7 0 message address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 24 23 16 15 8 7 0 message upper address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
pci-x con?uration space register description 6-27 copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0xxx message data read/write message data [15:0] system software initializes this register by writing to it. the LSIFC929X sends an interrupt message by writing a dword to the address held in the message address and message upper address registers. this register forms bits [15:0] of the dword message that the pci function passes to the host. the pci function drives bits [31:16] of this message to 0x0000. register: 0xxx pci-x capability id read only pci-x capability id [7:0] this register indicates the type of the current data structure. this register returns 0x07, indicating the pci-x data structure. 15 8 7 0 message data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 pci-x capability id 00000111
6-28 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0xxx pci-x next pointer read only pci-x next pointer [7:0] this register points to the next item in the capabilities list of this pci-x device. the value of this register varies according to system con?uration. register: 0xxx pci-x command read/write reserved [15:7] this ?ld is reserved. maximum outstanding split transactions [6:4] these bits indicate the maximum number of split transactions the LSIFC929X can have outstanding at one time. the LSIFC929X uses the most recent value of this register each time it prepares a new sequence. note that if the LSIFC929X prepares a sequence before the setting of this ?ld changes, the pci function initiates the prepared sequence with the previous setting. table 6.4 provides the bit encodings for this ?ld. 7 0 pci-x next pointer xxxxxxxx 15 8 7 0 pci-x command 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
pci-x con?uration space register description 6-29 copyright 2002, 2003 by lsi logic corporation. all rights reserved. maximum memory read byte count [3:2] these bits indicate the maximum byte count the LSIFC929X uses when initiating a sequence with one of the burst memory read commands. table 6.5 provides the bit encodings for this ?ld. reserved 1 this bit is reserved. data parity error recovery enable 0 the host device driver sets this bit to allow the LSIFC929X to attempt to recover from data parity errors. if the user clears this bit and the LSIFC929X is operating in the pci-x mode, the LSIFC929X asserts serr/ whenever the data parity error reported bit in the pci status register is set. table 6.4 maximum outstanding split transactions bits [6:4] encoding maximum outstanding split transactions 0b000 1 0b001 2 0b010 3 0b011 4 0b100 8 0b101 reserved 0b110 reserved 0b111 reserved table 6.5 maximum memory read byte count bits [3:2] encoding maximum memory read byte count 0b00 512 0b01 1024 0b10 2048 0b11 reserved
6-30 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0xxx pci-x status read/write reserved [31:30] this ?ld is reserved. received split completion error message 29 the LSIFC929X sets this bit upon receipt of a split completion message if the split completion error attribute bit is set. write a one (1) to this bit to clear it. designed maximum cumulative read size [28:26] these read-only bits indicate a number greater than or equal to the maximum cumulative size of all outstanding burst memory read transactions for the LSIFC929X pci device. the pci function must report the smallest value that correctly indicates its capability. the LSIFC929X reports 0b001 in this ?ld to indicate a designed maximum cumulative read size of 2 kbytes. designed maximum outstanding split transactions [25:23] these read-only bits indicate a number greater than or equal to the maximum number of all outstanding split transactions for the LSIFC929X pci device. the pci function must report the smallest value that correctly indicates its capability. the LSIFC929X reports 0b100 in this ?ld to indicate that the designed maximum number of outstanding split transactions is eight. designed maximum memory read byte count [22:21] these read-only bits indicate a number greater than or equal to the maximum byte count for the LSIFC929X pci device. the pci function uses this count to initiate a sequence with one of the burst memory read commands. the pci function must report the smallest value that 31 24 23 16 15 8 7 0 pci-x status 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 x x x x x x x x x x x x x x x x
pci-x con?uration space register description 6-31 copyright 2002, 2003 by lsi logic corporation. all rights reserved. correctly indicates its capability. the LSIFC929X reports 0b10 in this ?ld to indicate that the designed maximum memory read bytes count is 2048. device complexity 20 the pci function clears this read-only bit to indicate that the LSIFC929X is a simple device. unexpected split completion 19 the pci function sets this read-only bit when it receives an unexpected split completion. after this bit is set, this bit remains set until software clears it. write a one (1) to this bit to clear it. split completion discarded 18 the pci function sets this read-only bit when it discards a split completion. after this bit is set, this bit remains set until software clears it. write a one (1) to this bit to clear it. 133 mhz capable 17 the ma[8] power-on sense pin controls this read-only bit. allowing the internal pull-downs to pull ma[8] low sets this bit and enables 133 mhz operation of the pci bus. pulling ma[8] high clears this bit and disables 133 mhz operation of the pci bus. refer to table 4.3 on page 4-10 for details on the power-on sense pins. 64-bit device 16 the ma[9] power-on sense pin controls this read-only bit. allowing the internal pull-downs to pull ma[9] low sets this bit and indicates a 64-bit pci address/data bus. pulling ma[9] high clears this bit and indicates a 32-bit pci address/data bus. if using the LSIFC929X on an add-in card, this bit must indicate the size of the pci address/data bus on the card. refer to table 4.3 for details on the power-on sense pins. bus number [15:8] these read-only bits indicate the number of the LSIFC929X bus segment. this pci function uses this number as part of its requester id and completer id. this ?ld is read for diagnostic purposes only.
6-32 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. device number [7:3] these read-only bits indicate the device number of the LSIFC929X. this pci function uses this number as part of its requester id and completer id. this ?ld is read for diagnostic purposes only. function number [2:0] these read-only bits indicate the number in the function number ?ld (ad[10:8]) of a type 0 pci con?uration transaction. the pci function uses this number as part of its requester id and completer id. this ?ld is read for diagnostic purposes only. 6.2 pci i/o space and memory space register description this section describes the host interface registers in the pci i/o space and in the pci memory space. these address spaces contain the fusion-mpt interface register set. pci memory space [0] and pci memory space [1] form the pci memory space. pci memory space [0] supports normal memory accesses while pci memory space [1] supports diagnostic memory accesses. for all registers except the diagnostic read/write data and diagnostic read/write address registers, access the address offset through either pci i/o space or pci memory space [0]. access to the diagnostic read/write data and diagnostic read/write address registers is available only through pci i/o space. when the LSIFC929X operates as a multifunction pci device, the entire pci memory and pci i/o space register sets are visible to both pci functions. when the LSIFC929X operates as a single function pci device, only pci function [0] register sets are accessible.
pci i/o space and memory space register description 6-33 copyright 2002, 2003 by lsi logic corporation. all rights reserved. table 6.6 de?es the pci i/o space address map. table 6.7 de?es the pci memory space [0] address map. table 6.6 pci i/o space address map 31 16 15 0 offset page system doorbell 0x00 6-34 write sequence 0x04 6-35 host diagnostic 0x08 6-36 test base address 0x0c 6-38 diagnostic read/write data 0x10 6-38 diagnostic read/write address 0x14 6-39 reserved 0x18?x2f host interrupt status 0x30 6-40 host interrupt mask 0x34 6-41 reserved 0x38?x3f request fifo 0x40 6-42 reply fifo 0x44 6-43 reserved 0x48?x4c host index register 0x50 6-43 reserved 0x54?x7f table 6.7 pci memory [0] address map 31 16 15 0 offset page system doorbell 0x00 6-34 write sequence 0x04 6-35 host diagnostic 0x08 6-36 test base address 0x0c 6-38 reserved 0x10?x2f host interrupt status 0x30 6-40 host interrupt mask 0x34 6-41 reserved 0x38?x3f request fifo 0x40 6-42 reply fifo 0x44 6-43 reserved 0x48?x7f shared memory 0x80 0x(sizeof(mem0) ? 1)
6-34 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. table 6.8 de?es the pci memory space [1] address map. a bit-level description of the pci memory and pci i/o spaces follows. register: 0x00 system doorbell read/write this register is a simple message passing mechanism that allows the system to pass single word messages to the embedded iop processor and vice versa. there is a unique system doorbell for each pci function. when a host system pci master writes to the host registers doorbell register, the LSIFC929X generates a maskable interrupt to the iop. the value written by the host system is available for the iop to read in the system interface registers doorbell register. the iop clears the interrupt status after reading the value. conversely, when the iop processor writes to the system interface registers doorbell register, the LSIFC929X generates a maskable interrupt to the pci system. the host system can read the value written by the iop in the host registers doorbell register. the host system clears the interrupt status bit and interrupt pin by writing any value to the host registers interrupt status register. host doorbell value [31:0] during a write, this register contains the doorbell value that the host system passes to the iop. during a read, this register contains the doorbell value that the iop passes to the host system. table 6.8 pci memory [1] address map 31 16 15 0 diagnostic memory 0x00 0x(sizeof(mem1) ? 1) 31 24 23 16 15 8 7 0 system doorbell 00000000000000000000000000000000
pci i/o space and memory space register description 6-35 copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x04 write sequence read/write this register provides a protection mechanism against inadvertent writes to the host diagnostic register. there is one write i/o register that is visible to both pci functions. the two pci functions physically share this register. reserved [31:4] this ?ld is reserved. write i/o key [3:0] to enable write access to the diagnostic read/write data , diagnostic read/write address , and host diagnostic register, perform ve data-speci? writes to the write i/o key. writing an incorrect value to the write i/o key invalidates the key sequence, and the host must rewrite the entire sequence. the write i/o key sequence is: 0x0004, 0x000b, 0x0002, 0x0007, and 0x000d. to disable write access to the diagnostic read/write data , diagnostic read/write address , and host diagnostic registers, write any value (except the write i/o key sequence) to the write i/o register. the diagnostic write enable bit (bit 7 in the host diagnostic register) indicates the write access status. 31 24 23 16 15 8 7 0 write sequence 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01011
6-36 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x08 host diagnostic read/write this register contains diagnostic controls and status information. there is one host diagnostic register that is visible to both pci functions. the two pci functions physically share this register. however, the reset history bit operates independently for each pci function. this register can only be written when bit 7 of this register is set. reserved [31:12] this ?ld is reserved. bist read enable 11 setting this bit enables reading the two bist results registers (0x18 and 0x1c) from the host. clear flash bad signature 10 write this bit to clear the bad signature bit (bit 6 of this register). prevent iop boot 9 set this bit to keep the iop in a reset state. bist all done 8 when this bit is set, all internal built-in self-test (bist) operations are complete. diagnostic write enable 7 the LSIFC929X sets this read-only bit when the host writes the correct write i/o key to the write sequence register. the LSIFC929X clears this bit when the host writes a value other than the write i/o key to the write sequence register. flash bad signature 6 the LSIFC929X sets this bit if the iop arm966e-s processor encounters a bad flash signature when booting from flash rom. the LSIFC929X also sets the disarm bit (bit 1 in this register) to hold the iop arm 31 24 23 16 15 8 7 0 host diagnostic 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000001 00 0 x0
pci i/o space and memory space register description 6-37 copyright 2002, 2003 by lsi logic corporation. all rights reserved. processor in a reset state. the LSIFC929X maintains this state until the pci host clears both the flash bad signature and disarm bits. reset history 5 the LSIFC929X sets this bit if it experiences a power-on reset (por), pci reset, or testreset/. a host driver can clear this bit to help coordinate recovery between multiple driver instances in a multifunction pci implementation. diagnostic read/write enable 4 setting this bit enables access to the diagnostic read/write data and diagnostic read/write address registers. ttl interrupt 3 setting this bit con?ures pci inta/ as a ttl output. clearing this bit con?ures pci inta/ as an open-drain output. use this bit for test purposes only. reset adapter 2 setting this write-only bit causes a hard reset within the LSIFC929X. the bit self-clears after eight pci clock periods. after deasserting this bit, the iop arm processor executes from its default reset vector. disarm 1 setting this bit disables the iop arm processor. diagnostic memory enable 0 setting this bit enables diagnostic memory accesses through pci memory space [1]. clearing this bit disables diagnostic memory accesses to pci memory space [1] and returns 0xffff on reads.
6-38 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x0c test base address read/write this register speci?s the base address for memory space [1] accesses. there is one test base address register that is visible to both pci functions. the two pci functions physically share this register. because diagnostic memory is visible only to pci function [0], pci function [1] cannot write to this register. test base address [31:16] the number of signi?ant bits is determined by the size of pci memory space [1] in the serial eeprom. reserved [15:0] this ?ld is reserved. register: offset 0x10 diagnostic read/write data read/write this register reads or writes dword locations on the LSIFC929X internal bus. this register is only accessible through pci i/o space and returns 0xffffffff if read through pci memory space. the host can enable write access to this register by writing the correct write i/o key to the write sequence register and setting bit 4, the diagnostic write enable bit, of the host diagnostic register. a write of any value other than the correct write i/o key to the write sequence register disables write access to this register. there is one diagnostic read/write data register that is visible to both pci functions. the two pci functions physically share this register. 31 24 23 16 15 8 7 0 test base address 0000000000000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 24 23 16 15 8 7 0 diagnostic read/write data 00000000000000000000000000000000
pci i/o space and memory space register description 6-39 copyright 2002, 2003 by lsi logic corporation. all rights reserved. diagnostic read/write data [31:0] using this register, the LSIFC929X reads/writes data at the address that the diagnostic read/write address register speci?s. register: 0x14 diagnostic read/write address read/write this register speci?s a dword location on the internal bus. the address increments by a dword whenever the host system accesses the diagnostic read/write address register. this register is only accessible through pci i/o space and returns 0xffffffff if read through pci memory space. the host can enable write access to this register by writing the correct write i/o key to the write sequence register and setting bit 4, the diagnostic write enable bit, of the host diagnostic register. a write of any value other than the correct write i/o key to the write sequence register disables write access to this register. there is one diagnostic read/write address register that is visible to both pci functions. the two pci functions physically share this register. diagnostic read/write address [31:0] this register holds the address that the diagnostic read/write data register writes data to or reads data from. 31 24 23 16 15 8 7 0 diagnostic read/write address 00000000000000000000000000000000
6-40 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x30 host interrupt status read only this register provides read-only interrupt status information to the pci host. a write to this register of any value clears the associated system doorbell interrupt. there is a unique host interrupt status register for each pci function. iop doorbell status 31 the LSIFC929X sets this bit when the iop receives a message from the system doorbell but has yet to process it. the iop processes the system doorbell message by clearing the corresponding system request interrupt. reserved [30:4] this ?ld is reserved. reply interrupt 3 the LSIFC929X sets this bit when the reply post fifo is not empty. the LSIFC929X generates a pci interrupt when this bit is set and the corresponding mask bit in the host interrupt mask register is cleared. reserved [2:1] this ?ld is reserved. system doorbell interrupt 0 the LSIFC929X sets this bit when the iop writes a value to the system doorbell. the host can clear this bit by writing any value to this register. the LSIFC929X generates a pci interrupt when this bit is set and the corresponding mask bit in the host interrupt mask register is cleared. 31 24 23 16 15 8 7 0 host interrupt status 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x0 x x0
pci i/o space and memory space register description 6-41 copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x34 host interrupt mask read/write this register masks and/or routes the interrupt conditions that the host interrupt status register reports. there is a unique host interrupt mask register for each pci function. reserved [ 31:10] this ?ld is reserved. interrupt request routing mode [9:8] this ?ld routes pci interrupts to the intx/ pins according to the bit encodings in table 6.9 . if the host system enables msi, the LSIFC929X does not signal pci interrupts on the intx/ pins. note: the LSIFC929X does not support alternate interrupt signals (no device pins are provided). programming this ?ld to 0b10 effectively disables pci interrupts for the given pci function. reserved [7:4] this ?ld is reserved. 31 24 23 16 15 8 7 0 host interrupt mask x x x x x x x x x x x x x x x x x x x x x x00 x x x x1 x x1 table 6.9 interrupt signal routing bit [9:8] encodings interrupt signal routing 0b00 intx/ and alt_intx/ 0b01 intx/ only 0b10 alt_intx/ only 0b11 intx/ and alt_intx/
6-42 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. reply interrupt mask 3 setting this bit masks reply interrupts and prevents the assertion of a pci interrupt for all reply interrupt conditions. reserved [2:1] this ?ld is reserved. doorbell interrupt mask 0 setting this bit masks system doorbell interrupts and prevents the assertion of a pci interrupt for all system doorbell interrupt conditions. register: 0x40 request fifo read/write this register provides request free message frame addresses (mfas) to the host system on reads and accepts request post mfas from the host system on writes. there is one request fifo register that is visible to both pci functions. the two pci functions physically share this register. request fifo [ 31:0] for reads, the request free mfa is empty and this register contains 0xffffffff. for writes, the register contains the request post mfa. 31 24 23 16 15 8 7 0 request fifo 11111111111111111111111111111111
pci i/o space and memory space register description 6-43 copyright 2002, 2003 by lsi logic corporation. all rights reserved. register: 0x44 reply fifo read/write this register provides reply post mfas to the host system on reads and accepts reply free mfas from the host system on writes. there is one unique reply fifo register for each pci function. reply fifo [31:0] for reads, the request free mfa is empty and this register contains 0xffffffff. for writes, the register contains the reply free mfa. register: 0x50 host index register read/write these registers are used with the outbound reply option (altreplypost method) to enable host-resident reply post queues. reserved [31:14] this ?ld is reserved. host index value [13:0] the host index provides an indication of which reply post mfas the host system has processed, and generates reply interrupts when the altreplypost option is enabled. there is a unique host index register associated with each pci function. 31 24 23 16 15 8 7 0 reply fifo 11111111111111111111111111111111 31 24 23 16 15 8 7 0 reply fifo 11111111111111111111111111111111
6-44 registers copyright 2002, 2003 by lsi logic corporation. all rights reserved. 6.3 shared memory a region of shared memory (LSIFC929X local memory mapped to system addresses) is provided to allow the host to write request message frames. this is the default method (push model) for request message frame transport, where the host itself copies the request message frame into the LSIFC929X local memory. the total size of shared memory is con?ured by the i/o processor (iop) on reset. supported values are 32 kbytes, 64 kbytes, 128 kbytes (default), 256 kbytes, and 512 kbytes. shared memory is accessible only through mem0 space starting at address 0x080.
LSIFC929X dual channel fibre channel i/o processor technical manual 7-1 copyright 2002, 2003 by lsi logic corporation. all rights reserved. chapter 7 speci?ations this chapter provides a description of the dc and ac electrical characteristics of the LSIFC929X dual channel fibre channel i/o processor chip, and the available packaging. the chapter contains the following sections: ? section 7.1, ?lectrical requirements ? section 7.2, ?c timing ? section 7.3, ?ackaging ? section 7.4, ?echanical drawing ? section 7.5, ?ackage thermal considerations
7-2 speci?ations copyright 2002, 2003 by lsi logic corporation. all rights reserved. 7.1 electrical requirements table 7.1 provides absolute maximum stress ratings for the LSIFC929X, while table 7.2 speci?s the normal operating conditions. table 7.3 through table 7.9 specify the input and output electrical characteristics .
electrical requirements 7-3 copyright 2002, 2003 by lsi logic corporation. all rights reserved. table 7.1 absolute maximum stress ratings 1 1. stresses beyond those listed in this table may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the operating conditions section of the manual is not implied. symbol parameter min max unit test conditions t stg storage temperature ? 55 150 ?c v dd supply voltage ? 0.5 4.5 v v in input voltage v ss ? 0.3 v dd + 0.3 v i lp 2 2. ? 3vLSIFC929X. core supply voltage 1.71 1.89 v v ddio i/o supply voltage 3.13 3.47 v pci5vref pci 5 v reference voltage 4.75 5.25 vddio v v 5 v pci system 3.3 v pci system t a operating free air 0 70 ?c jma 3 3. jmamax (junction-to-moving air thermal resistance) assumes a 4-layer package substrate, a 456-pad pbga, and a 4-layer pcb design (10?2 watt/meter ?k). this maximum number is the worst-case jma for the LSIFC929X with no heat sink and no air ?w. refer to section 7.5, ?ackage thermal considerations, on page 7-19 for details. thermal resistance (junction to moving air) 15.3 ?c/w
7-4 speci?ations copyright 2002, 2003 by lsi logic corporation. all rights reserved. table 7.3 capacitance symbol parameter min max unit test conditions c i input capacitance of input pads 7 pf c io input capacitance of i/o pads 10 pf table 7.4 input signals (fault1/, fault0/, mode[7:0], switch, hotswapen/) symbol parameter min max unit test conditions v ih input high voltage 0.7 v dd v dd + 0.3 v v il input low voltage v ss ? 0.3 0.2 v dd v i in input leakage 10 10 a table 7.5 schmitt input signals (refclk, tck, tdi, trst/, tms_chip, tms_ice) symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage v ss ? 0.3 0.8 v i in input leakage 10 10 a table 7.6 4 ma bidirectional signals (lipreset/, odis1, odis0, bypass1/, bypass0/, md[31:0], ma[21:0], mwe[1:0]/, flashcs/, bwe[3:0]/, ramcs/, zz, mp[3:0], scl, sda, rxlos1, rxlos0, adsc/, adv/, tdo) symbol parameter min max unit test conditions v ih input high voltage 0.7 v dd v dd + 0.3 v v il input low voltage v ss ? 0.3 0.2 v dd v v oh output high voltage 2.4 v dd v ? 4ma v ol output low voltage v ss 0.4 v 4 ma i oz 3-state leakage ? 10 10 a
electrical requirements 7-5 copyright 2002, 2003 by lsi logic corporation. all rights reserved. table 7.7 8 ma bidirectional signals (moddef1[2:0], moddef0[2:0], gpio[5:0], moe[1:0]/, led[4:0]/, mclk) symbol parameter min max unit test conditions v ih input high voltage 0.7 v dd v dd + 0.3 v v il input low voltage v ss ? 0.3 0.2 v dd v v oh output high voltage 2.4 v dd v ? 8ma v ol output low voltage v ss 0.4 v 8 ma i oz 3-state leakage ? 10 10 a table 7.8 pci input signals (pciclk, gnt/, idsel, rst/) symbol parameter min max unit test conditions v ih input high voltage 2.0 0.5 v dd v dd + 0.5 5.5 v v 5 v pci system 3.3 v pci system v il input low voltage ? 0.5 ? 0.5 0.8 0.3 v dd v v 5 v pci system 3.3 v pci system
7-6 speci?ations copyright 2002, 2003 by lsi logic corporation. all rights reserved. table 7.9 pci bidirectional signals (ad[63:0], c_be[7:0]/, frame/, irdy/, trdy/, stop/, perr/, par, ack64/, enum/, 64en/) symbol parameter min max unit test conditions v ih input high voltage 2.0 0.5 v dd v dd + 0.5 5.5 v v 5 v pci system 3.3 v pci system v il input low voltage ? 0.5 ? 0.5 0.8 0.3 v dd v v 5 v pci system 3.3 v pci system v oh output high voltage 0.9 v dd v dd v ? 0.5 ma (3.3 v pci) v oh output high voltage 2.4 v ? 2 ma (5 v pci) v ol output low voltage v ss 0.1 v dd v 1.5 ma (3.3 v pci) v ol output low voltage 0.55 v 3 ma, 6 ma (5 v pci) 1 1. signals without pull-up resistors meet a 3 ma output current load. signals requiring pull-ups meet a 6 ma output current load. the latter include frame/ , trdy/ , irdy/ , stop/ , perr/ , and, when used, ad[63:32] , c_be[7:4] , and ack64/ . i oz 3-state leakage ? 10 10 a table 7.10 pci output signals (par64, req/, req64/, devsel/, serr/, inta/, intb/) symbol parameter min max unit test conditions v oh output high voltage 0.9 v dd v dd v ? 0.5 ma (3.3 v pci) v oh output high voltage 2.4 v ? 2 ma (5 v pci) v ol output low voltage v ss 0.1 v dd v 1.5 ma (3.3 v pci) v ol output low voltage 0.55 v 3 ma, 6 ma (5 v pci) 1 1. signals without pull-up resistors meet a 3 ma output current load. signals requiring pull-ups meet a 6 ma output current load. the latter include devsel/ , serr/ , inta/ , intb/ , and, when used, par64 , and req64/ . i oz 3-state leakage ? 10 10 a
ac timing 7-7 copyright 2002, 2003 by lsi logic corporation. all rights reserved. 7.2 ac timing the ac timing characteristics described in this section apply over the entire range of operating conditions. chip timings are based on simulation at worst-case voltage, temperature, and processing. timings have been developed with a load capacitance of 50 pf. 7.2.1 pci/pci-x interface timings the LSIFC929X pci/pci-x signals conform to the electrical and timing standards as shown in the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a . all hardware validation testing performed by lsi logic guarantees that the LSIFC929X meets or exceeds the speci?ations contained in those documents. 7.2.2 fibre channel interface timings the LSIFC929X receiver and transmitter serial differential signal pairs conform to the electrical and timing standards as shown in the fibre channel physical interface speci?ation (fc-pi, rev. 11). all hardware validation testing performed by lsi logic guarantees that the LSIFC929X meets or exceeds the speci?ations contained in that document.
7-8 speci?ations copyright 2002, 2003 by lsi logic corporation. all rights reserved. 7.2.3 memory interface timings 7.2.3.1 ssram timings figure 7.1 ssram read/write/read timing waveforms mclk ma/ctl md moe[0]/ moe[1]/ addr(x) adsc addr(y) adsc addr(y) addr (y+1) addr(z) adsc addr(z) addr(z) addr addr(z+2) (z+1) read data invalid data(y) data (y+1) read data(z+2) read data(z+1) read data(z) t cyc t wdv t wdh rd deselect and bus wr address and select wr data wr data wr deselect, rd address, and select rd pipe wait rd data rd data turnaround t rsu t rh t enov t ohz t olz t oev table 7.11 ssram read/write/read timings symbol parameter min max unit t cyc mclk cycle time 14.115 14.119 ns t rsu read setup time 7 ns t rh read hold time 0 ns t wdv write valid time 10 ns t wdh write hold time 2 ns t oev output enable valid 8 ns t olz data low impedance 2.5 12 ns t ohz data high impedance 2 12 ns t enov output enable nonoverlap 0 ns
ac timing 7-9 copyright 2002, 2003 by lsi logic corporation. all rights reserved. 7.2.3.2 flash rom timings figure 7.2 flash rom read timing waveforms mclk ma md flashcs/ moe[1]/ addr(?) addr(x) addr(y) read/write data t cyc idle or s-xfer f-addr f-addr f-wait(n) f-data f-turn f-turn f-addr t hz t as data(x) t rh bwe[3]/ m-state n = 16 t rs t ah f-addr table 7.12 flash rom read timings symbol parameter min max unit t cyc mclk cycle time 14.115 14.119 ns t as address setup time ? 5.0 1 1. address setup time defaults to one (1) mclk but may be programmed to zero (0) mclks using the serial eeprom. 1 mclk 2 ns t ah address hold time 0 ns t rs read setup time 7 ns t rh read hold time 0 ns t hz data high impedance 0 32 ns
7-10 speci?ations copyright 2002, 2003 by lsi logic corporation. all rights reserved. figure 7.3 flash rom write timing waveforms addr(? addr(x) addr(y) read/write data t cyc idle or s-xfer f-addr f-addr f-wait(n) f-data idle f-addr f-addr data(x) n = 16 t as data(y) t ws t ah t wh f-turn mclk ma md flashcs/ moe[1]/ bwe[3]/ m-state table 7.13 flash rom write timings symbol parameter min max unit t cyc mclk cycle time 14.115 14.119 ns t as address setup time ? 5.0 1 1. address setup time defaults to one (1) mclk but may be programmed to zero (0) mclks using the serial eeprom. 1 mclk 2 ns t ah address hold time 1 mclk ns t ws write setup time 3 2 2. programmed using the serial eeprom. 11 3 mclk t wh write hold time 1 mclk ns
packaging 7-11 copyright 2002, 2003 by lsi logic corporation. all rights reserved. 7.3 packaging figure 7.4 illustrates the signal locations for the 456 plastic ball grid array (pbga). table 7.14 on page 7-14 lists the LSIFC929X signals in alphanumeric order by pbga position. table 7.15 on page 7-16 lists the LSIFC929X signals alphanumerically by signal name. figure 7.5 on page 7-18 is the mechanical drawing of the package for the LSIFC929X.
7-12 speci?ations copyright 2002, 2003 by lsi logic corporation. all rights reserved. figure 7.4 LSIFC929X 456-pin pbga top view a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 vssio vddio nc mode[7] mode[5] test[0] moddef0[1] rxlos0 txvdd0 tx0 ? nc rx0 ? rxbvss0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 vddio mode[3] led[4]/ led[1]/ test[1] nc odis0 fault0/ txvss0 tx0+ nc rx0+ rxbvdd0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 refclk mode[1] mode[6] vssio vssc test[8] vddio vssio vddc vssc vddio vssio rtrim d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 nc ref- pllvdd vddio mode[4] vddc led[2]/ led[0]/ bypass0/ moddef0[2] txbvss0 txbvdd0 rxvss0 rxvdd0 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 e11 e12 e13 mode[2] vssio mode[0] vssc vssio vddio led[3]/ test[2] vssio vddio moddef0[0] vssc vssio f1 f2 f3 f4 f5 test[5] nc test[6] nc vddio g1 g2 g3 g4 g5 nc nc vssio refpllvss vddc h1 h2 h3 h4 h5 nc gpio[3] vddio vssc test[7] j1 j2 j3 j4 j5 gpio[0] gpio[5] gpio[1] vddc vssio k1 k2 k3 k4 k5 gpio[2] (blueled/) nc gpio[4] nc vddio l1 l2 l3 l4 l5 l11 l12 l13 test[3] tck vssio tms_chip vssc vssio vssio vssio m1 m2 m3 m4 m5 m11 m12 m13 nc trst/ vddio tdo vddc vssio vssio vssio n1 n2 n3 n4 n5 n11 n12 n13 tms_ice test[4] test[9] tdi vssio vssio vssio vssio p1 p2 p3 p4 p5 p11 p12 p13 64en/ nc bzrset enum/ vddio vssio vssio vssio r1 r2 r3 r4 r5 r11 r12 r13 switch nc vssio bzvdd vddc vssio vssio vssio t1 t2 t3 t4 t5 t11 t12 t13 hot- swapen/ intb/ vddio inta/ vssc vssio vssio vssio u1 u2 u3 u4 u5 v5pcix v5pcix rst/ gnt/ vssio v1 v2 v3 v4 v5 pciclk req/ ad[31] vssc vddio w1 w2 w3 w4 w5 ad[30] ad[29] vssio ad[22] ad[28] y1 y2 y3 y4 y5 ad[27] ad[26] vddio ad[25] vssc aa1 aa2 aa3 aa4 aa5 vddc c_be[3]/ idsel ad[23] vssio ab1 ab2 ab3 ab4 ab5 ab6 ab7 ab8 ab9 ab10 ab11 ab12 ab13 ad[24] ad[21] vddio vddc vddio vssio vddc vssc vddio vssio vddc vssc vddio ac1 ac2 ac3 ac4 ac5 ac6 ac7 ac8 ac9 ac10 ac11 ac12 ac13 ad[20] v5pcix ad[19] vssio vssc devsel/ v5pcix ad[15] vddc ad[8] ad[7] ad[4] ad[0] ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 v5pcix ad[18] pcipllvdd pcipllvss vddio stop/ vssio vddio ad[12] c_be[0]/ vssio vddio ad[2] ae1 ae2 ae3 ae4 ae5 ae6 ae7 ae8 ae9 ae10 ae11 ae12 ae13 vssio v5pcix ad[16] c_be[2]/ irdy/ perr/ par ad[14] ad[11] ad[9] nc ad[6] ad[3] af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 vddio vssio frame/ trdy/ serr/ ad[17] c_be[1]/ ad[13] v5pcix ad[10] v5pcix v5pcix ad[5]
packaging 7-13 copyright 2002, 2003 by lsi logic corporation. all rights reserved. figure 7.4 LSIFC929X 456-pin pbga top view (cont.) a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 txbvss1 tx1 ? nc rx1 ? rxvdd1 rxlos1 mod- def1[1] sda md[5] md[8] md[11] vssio vddio b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 txbvdd1 tx1+ nc rx1+ rxvss1 fault1/ odis1 scl md[4] md[7] md[10] md[12] vssio c14 c15 c16 c17 c18 c19 c20 c21 c22 c23 c24 c25 c26 lipreset/ vddio vssio vssc vddc vddio vssio md[3] vssc vddio md[9] md[13] md[14] d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 txvdd1 txvss1 rxbvdd1 rxbvss1 mod- def1[0] bypass1/ md[1] md[2] vddc md[6] vssio md[15] mp[1] e14 e15 e16 e17 e18 e19 e20 e21 e22 e23 e24 e25 e26 vddio vddc mod- def1[2] vssio vddio mp[0] md[0] vssio vddio vssc flashcs/ vddio moe[0]/ f22 f23 f24 f25 f26 vssio zz ramcs/ mwe[0]/ moe[1]/ g22 g23 g24 g25 g26 vddc mwe[1]/ vddio bwe[0]/ bwe[1]/ h22 h23 h24 h25 h26 vssc bwe[2]/ vssio bwe[3]/ adv/ j22 j23 j24 j25 j26 vddio vddc mp[2] adsc/ mclk k22 k23 k24 k25 k26 vssio md[16] md[17] md[18] md[19] l14 l15 l16 l22 l23 l24 l25 l26 vssio vssio vssio vssc md[20] vddio md[21] md[22] m14 m15 m16 m22 m23 m24 m25 m26 vssio vssio vssio vddc md[23] vssio md[24] md[25] n14 n15 n16 n22 n23 n24 n25 n26 vssio vssio vssio vddio md[26] md[27] md[28] md[29] p14 p15 p16 p22 p23 p24 p25 p26 vssio vssio vssio vssio md[30] md[31] mp[3] vssc r14 r15 r16 r22 r23 r24 r25 r26 vssio vssio vssio ma[0] ma[1] vddio ma[2] ma[3] t14 t15 t16 t22 t23 t24 t25 t26 vssio vssio vssio vddc ma[4] vssio ma[5] ma[6] u22 u23 u24 u25 u26 vddio ma[7] ma[8] ma[9] ma[10] v22 v23 v24 v25 v26 vssio vssc ma[11] ma[12] ma[13] w22 w23 w24 w25 w26 vddc ma[14] vddio ma[15] ma[16] y22 y23 y24 y25 y26 vssc ad[32] vssio ma[17] ma[18] aa22 aa23 aa24 aa25 aa26 vddio ad[33] nc ma[19] ad[35] ab14 ab15 ab16 ab17 ab18 ab19 ab20 ab21 ab22 ab23 ab24 ab25 ab26 vssio vssc vddc vddio vssio vssc vddc vddio vssio vddc ad[34] vssio ma[20] ac14 ac15 ac16 ac17 ac18 ac19 ac20 ac21 ac22 ac23 ac24 ac25 ac26 c_be[7]/ ad[1] v5pcix ad[60] vddc ad[55] ad[51] ad[46] vssc v5pcix vddio ad[36] ma[21] ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 req64/ vssio vddio ad[61] ad[57] vssio vddio ad[48] ad[44] vssio ad[37] ad[39] ad[38] ae14 ae15 ae16 ae17 ae18 ae19 ae20 ae21 ae22 ae23 ae24 ae25 ae26 ack64/ c_be[5]/ ad[63] ad[62] ad[58] ad[54] ad[52] ad[49] ad[45] ad[42] ad[41] ad[40] vddio af14 af15 af16 af17 af18 af19 af20 af21 af22 af23 af24 af25 af26 c_be[4]/ c_be[6]/ par64 v5pcix ad[59] ad[56] ad[53] ad[50] ad[47] ad[43] v5pcix vddio vssio
7-14 speci?ations copyright 2002, 2003 by lsi logic corporation. all rights reserved. table 7.14 alphanumeric pad listing by pbga position p23 md[30] p24 md[31] p25 mp[3] p26 vssc r1 switch r2 nc r3 vssio r4 bzvdd r5 vddc r11 vssio r12 vssio r13 vssio r14 vssio r15 vssio r16 vssio r22 ma[0] r23 ma[1] r24 vddio r25 ma[2] r26 ma[3] t1 hotswapen/ t2 intb/ t3 vddio t4 inta/ t5 vssc t11 vssio t12 vssio t13 vssio t14 vssio t15 vssio t16 vssio t22 vddc t23 ma[4] t24 vssio t25 ma[5] t26 ma[6] u1 v5pcix u2 v5pcix u3 rst/ u4 gnt/ u5 vssio u22 vddio u23 ma[7] u24 ma[8] u25 ma[9] u26 ma[10] v1 pciclk v2 req/ v3 ad[31] v4 vssc v5 vddio v22 vssio v23 vssc v24 ma[11] v25 ma[12] v26 ma[13] w1 ad[30] w2 ad[29] w3 vssio ball # signal ball # signal a1 vssio a2 vddio a3 nc 1 a4 mode[7] a5 mode[5] a6 test[0] a7 moddef0[1] a8 rxlos0 a9 txvdd0 a10 tx0 ? a11 nc a12 rx0- a13 rxbvss0 a14 txbvss1 a15 tx1 ? a16 nc a17 rx1 ? a18 rxvdd1 a19 rxlos1 a20 moddef1[1] a21 sda a22 md[5] a23 md[8] a24 md[11] a25 vssio a26 vddio b1 vddio b2 mode[3] b3 led[4]/ b4 led[1]/ b5 test[1] b6 nc b7 odis0 b8 fault0/ b9 txvss0 b10 tx0+ b11 nc b12 rx0+ b13 rxbvdd0 b14 txbvdd1 b15 tx1+ b16 nc b17 rx1+ b18 rxvss1 b19 fault1/ b20 odis1 b21 scl b22 md[4] b23 md[7] b24 md[10] b25 md[12] b26 vssio c1 refclk c2 mode[1] c3 mode[6] c4 vssio c5 vssc c6 test[8] c7 vddio c8 vssio c9 vddc c10 vssc c11 vddio c12 vssio c13 rtrim c14 lipreset/ c15 vddio c16 vssio c17 vssc c18 vddc c19 vddio c20 vssio c21 md[3] c22 vssc c23 vddio c24 md[9] c25 md[13] c26 md[14] d1 nc d2 refpllvdd d3 vddio d4 mode[4] d5 vddc d6 led[2]/ d7 led[0]/ d8 bypass0/ d9 moddef0[2] d10 txbvss0 d11 txbvdd0 d12 rxvss0 d13 rxvdd0 d14 txvdd1 d15 txvss1 d16 rxbvdd1 d17 rxbvss1 d18 moddef1[0] d19 bypass1/ d20 md[1] d21 md[2] d22 vddc d23 md[6] d24 vssio d25 md[15] d26 mp[1] e1 mode[2] e2 vssio e3 mode[0] e4 vssc e5 vssio e6 vddio e7 led[3]/ e8 test[2] e9 vssio e10 vddio e11 moddef0[0] e12 vssc e13 vssio e14 vddio e15 vddc e16 moddef1[2] e17 vssio e18 vddio e19 mp[0] e20 md[0] e21 vssio e22 vddio e23 vssc e24 flashcs/ e25 vddio e26 moe[0]/ f1 test[5] f2 nc f3 test[6] f4 nc f5 vddio f22 vssio f23 zz f24 ramcs/ f25 mwe[0]/ f26 moe[1]/ g1 nc g2 nc g3 vssio g4 refpllvss g5 vddc g22 vddc g23 mwe[1]/ g24 vddio g25 bwe[0]/ g26 bwe[1]/ h1 nc h2 gpio[3] h3 vddio h4 vssc h5 test[7] h22 vssc h23 bwe[2]/ h24 vssio h25 bwe[3]/ h26 adv/ j1 gpio[0] j2 gpio[5] j3 gpio[1] j4 vddc j5 vssio j22 vddio j23 vddc j24 mp[2] j25 adsc/ j26 mclk k1 gpio[2](blueled/) k2 nc k3 gpio[4] k4 nc k5 vddio k22 vssio k23 md[16] k24 md[17] k25 md[18] k26 md[19] l1 test[3] l2 tck l3 vssio l4 tms_chip l5 vssc l11 vssio l12 vssio l13 vssio l14 vssio l15 vssio l16 vssio l22 vssc l23 md[20] l24 vddio l25 md[21] l26 md[22] m1 nc m2 trst/ m3 vddio m4 tdo m5 vddc m11 vssio m12 vssio m13 vssio m14 vssio m15 vssio m16 vssio m22 vddc m23 md[23] m24 vssio m25 md[24] m26 md[25] n1 tms_ice n2 test[4] n3 test[9] n4 tdi n5 vssio n11 vssio n12 vssio n13 vssio n14 vssio n15 vssio n16 vssio n22 vddio n23 md[26] n24 md[27] n25 md[28] n26 md[29] p1 64en/ p2 nc p3 bzrset p4 enum/ p5 vddio p11 vssio p12 vssio p13 vssio p14 vssio p15 vssio p16 vssio p22 vssio ball # signal ball # signal ball # signal 1. nc pins are not connected.
packaging 7-15 copyright 2002, 2003 by lsi logic corporation. all rights reserved. table 7.14 alphanumeric pad listing by pbga position (cont.) ae24 ad[41] ae25 ad[40] ae26 vddio af1 vddio af2 vssio af3 frame/ af4 trdy/ af5 serr/ af6 ad[17] af7 c_be[1]/ af8 ad[13] af9 v5pcix af10 ad[10] af11 v5pcix af12 v5pcix af13 ad[5] af14 c_be[4]/ af15 c_be[6]/ af16 par64 af17 v5pcix af18 ad[59] af19 ad[56] af20 ad[53] af21 ad[50] af22 ad[47] af23 ad[43] af24 v5pcix af25 vddio af26 vssio ball # signal ball # signal w4 ad[22] w5 ad[28] w22 vddc w23 ma[14] w24 vddio w25 ma[15] w26 ma[16] y1 ad[27] y2 ad[26] y3 vddio y4 ad[25] y5 vssc y22 vssc y23 ad[32] y24 vssio y25 ma[17] y26 ma[18] aa1 vddc aa2 c_be[3]/ aa3 idsel aa4 ad[23] aa5 vssio aa22 vddio aa23 ad[33] aa24 nc 1 aa25 ma[19] aa26 ad[35] ab1 ad[24] ab2 ad[21] ab3 vddio ab4 vddc ab5 vddio ab6 vssio ab7 vddc ab8 vssc ab9 vddio ab10 vssio ab11 vddc ab12 vssc ab13 vddio ab14 vssio ab15 vssc ab16 vddc ab17 vddio ab18 vssio ab19 vssc ab20 vddc ab21 vddio ab22 vssio ab23 vddc ab24 ad[34] ab25 vssio ab26 ma[20] ac1 ad[20] ac2 v5pcix ac3 ad[19] ac4 vssio ac5 vssc ac6 devsel/ ac7 v5pcix ac8 ad[15] ac9 vddc ac10 ad[8] ac11 ad[7] ac12 ad[4] ac13 ad[0] ac14 c_be[7]/ ac15 ad[1] ac16 v5pcix ac17 ad[60] ac18 vddc ac19 ad[55] ac20 ad[51] ac21 ad[46] ac22 vssc ac23 v5pcix ac24 vddio ac25 ad[36] ac26 ma[21] ad1 v5pcix ad2 ad[18] ad3 pcipllvdd ad4 pcipllvss ad5 vddio ad6 stop/ ad7 vssio ad8 vddio ad9 ad[12] ad10 c_be[0]/ ad11 vssio ad12 vddio ad13 ad[2] ad14 req64/ ad15 vssio ad16 vddio ad17 ad[61] ad18 ad[57] ad19 vssio ad20 vddio ad21 ad[48] ad22 ad[44] ad23 vssio ad24 ad[37] ad25 ad[39] ad26 ad[38] ae1 vssio ae2 v5pcix ae3 ad[16] ae4 c_be[2]/ ae5 irdy/ ae6 perr/ ae7 par ae8 ad[14] ae9 ad[11] ae10 ad[9] ae11 nc ae12 ad[6] ae13 ad[3] ae14 ack64/ ae15 c_be[5]/ ae16 ad[63] ae17 ad[62] ae18 ad[58] ae19 ad[54] ae20 ad[52] ae21 ad[49] ae22 ad[45] ae23 ad[42] ball # signal ball # signal ball # signal 1. nc pins are not connected.
7-16 speci?ations copyright 2002, 2003 by lsi logic corporation. all rights reserved. table 7.15 alphanumeric pad listing by signal name tdi n4 tdo m4 test[0] a6 test[1] b5 test[2] e8 test[3] l1 test[4] n2 test[5] f1 test[6] f3 test[7] h5 test[8] c6 test[9] n3 tms_chip l4 tms_ice n1 trdy/ af4 trst/ m2 tx0- a10 tx0+ b10 tx1- a15 tx1+ b15 txbvdd0 d11 txbvdd1 b14 txbvss0 d10 txbvss1 a14 txvdd0 a9 txvdd1 d14 txvss0 b9 txvss1 d15 v5pcix u1 v5pcix u2 v5pcix ac2 v5pcix ac7 v5pcix ac16 v5pcix ac23 v5pcix ad1 v5pcix ae2 v5pcix af9 v5pcix af11 v5pcix af12 v5pcix af17 v5pcix af24 vddc c9 vddc c18 vddc d5 vddc d22 vddc e15 vddc g5 vddc g22 vddc j4 vddc j23 vddc m5 vddc m22 vddc r5 vddc t22 vddc w22 vddc aa1 vddc ab4 vddc ab7 vddc ab11 signal ball #l signal ball # 64en/ p1 ack64/ ae14 ad[0] ac13 ad[1] ac15 ad[2] ad13 ad[3] ae13 ad[4] ac12 ad[5] af13 ad[6] ae12 ad[7] ac11 ad[8] ac10 ad[9] ae10 ad[10] af10 ad[11] ae9 ad[12] ad9 ad[13] af8 ad[14] ae8 ad[15] ac8 ad[16] ae3 ad[17] af6 ad[18] ad2 ad[19] ac3 ad[20] ac1 ad[21] ab2 ad[22] w4 ad[23] aa4 ad[24] ab1 ad[25] y4 ad[26] y2 ad[27] y1 ad[28] w5 ad[29] w2 ad[30] w1 ad[31] v3 ad[32] y23 ad[33] aa23 ad[34] ab24 ad[35] aa26 ad[36] ac25 ad[37] ad24 ad[38] ad26 ad[39] ad25 ad[40] ae25 ad[41] ae24 ad[42] ae23 ad[43] af23 ad[44] ad22 ad[45] ae22 ad[46] ac21 ad[47] af22 ad[48] ad21 ad[49] ae21 ad[50] af21 ad[51] ac20 ad[52] ae20 ad[53] af20 ad[54] ae19 ad[55] ac19 ad[56] af19 ad[57] ad18 ad[58] ae18 ad[59] af18 ad[60] ac17 ad[61] ad17 ad[62] ae17 ad[63] ae16 adsc/ j25 adv/ h26 bwe[0]/ g25 bwe[1]/ g26 bwe[2]/ h23 bwe[3]/ h25 bypass0/ d8 bypass1/ d19 bzrset p3 bzvdd r4 c_be[0]/ ad10 c_be[1]/ af7 c_be[2]/ ae4 c_be[3]/ aa2 c_be[4]/ af14 c_be[5]/ ae15 c_be[6]/ af15 c_be[7]/ ac14 devsel/ ac6 enum/ p4 fault0/ b8 fault1/ b19 flashcs/ e24 frame/ af3 gnt/ u4 gpio[0] j1 gpio[1] j3 gpio[2](blueled/) k1 gpio[3] h2 gpio[4] k3 gpio[5] j2 hotswapen/ t1 idsel aa3 inta/ t4 intb/ t2 irdy/ ae5 led[0]/ d7 led[1]/ b4 led[2]/ d6 led[3]/ e7 led[4]/ b3 lipreset/ c14 ma[0] r22 ma[1] r23 ma[2] r25 ma[3] r26 ma[4] t23 ma[5] t25 ma[6] t26 ma[7] u23 ma[8] u24 ma[9] u25 ma[10] u26 ma[11] v24 ma[12] v25 ma[13] v26 ma[14] w23 ma[15] w25 ma[16] w26 ma[17] y25 ma[18] y26 ma[19] aa25 ma[20] ab26 ma[21] ac26 mclk j26 md[0] e20 md[1] d20 md[2] d21 md[3] c21 md[4] b22 md[5] a22 md[6] d23 md[7] b23 md[8] a23 md[9] c24 md[10] b24 md[11] a24 md[12] b25 md[13] c25 md[14] c26 md[15] d25 md[16] k23 md[17] k24 md[18] k25 md[19] k26 md[20] l23 md[21] l25 md[22] l26 md[23] m23 md[24] m25 md[25] m26 md[26] n23 md[27] n24 md[28] n25 md[29] n26 md[30] p23 md[31] p24 moddef0[0] e11 moddef0[1] a7 moddef0[2] d9 moddef1[0] d18 moddef1[1] a20 moddef1[2] e16 mode[0] e3 mode[1] c2 mode[2] e1 mode[3] b2 mode[4] d4 mode[5] a5 mode[6] c3 mode[7] a4 moe[0]/ e26 moe[1]/ f26 mp[0] e19 mp[1] d26 mp[2] j24 mp[3] p25 mwe[1]/ g23 mwe[0]/ f25 nc 1 a3 nc a11 nc a16 nc b6 nc b11 nc b16 nc d1 nc f2 nc f4 nc g1 nc g2 nc h1 nc k2 nc k4 nc m1 nc p2 nc r2 nc aa24 nc ae11 odis0 b7 odis1 b20 par ae7 par64 af16 pciclk v1 pcipllvdd ad3 pcipllvss ad4 perr/ ae6 ramcs/ f24 refclk c1 refpllvdd d2 refpllvss g4 req/ v2 req64/ ad14 rst/ u3 rtrim c13 rx0 ? a12 rx0+ b12 rx1 ? a17 rx1+ b17 rxbvdd0 b13 rxbvdd1 d16 rxbvss0 a13 rxbvss1 d17 rxlos0 a8 rxlos1 a19 rxvdd0 d13 rxvdd1 a18 rxvss0 d12 rxvss1 b18 scl b21 sda a21 serr/ af5 stop/ ad6 switch r1 tck l2 signal ball # signal ball # signal ball # 1. nc pins are not connected.
packaging 7-17 copyright 2002, 2003 by lsi logic corporation. all rights reserved. table 7.15 alphanumeric pad listing by signal name (cont.) vssio r16 vssio t11 vssio t12 vssio t13 vssio t14 vssio t15 vssio t16 vssio t24 vssio u5 vssio v22 vssio w3 vssio y24 vssio aa5 vssio ab6 vssio ab10 vssio ab14 vssio ab18 vssio ab22 vssio ab25 vssio ac4 vssio ad7 vssio ad11 vssio ad15 vssio ad19 vssio ad23 vssio ae1 vssio af2 vssio af26 zz f23 signal ball # signal ball # vddc ab16 vddc ab20 vddc ab23 vddc ac9 vddc ac18 vddio a2 vddio a26 vddio b1 vddio c7 vddio c11 vddio c15 vddio c19 vddio c23 vddio d3 vddio e6 vddio e10 vddio e14 vddio e18 vddio e22 vddio e25 vddio f5 vddio g24 vddio h3 vddio j22 vddio k5 vddio l24 vddio m3 vddio n22 vddio p5 vddio r24 vddio t3 vddio u22 vddio v5 vddio w24 vddio y3 vddio aa22 vddio ab3 vddio ab5 vddio ab9 vddio ab13 vddio ab17 vddio ab21 vddio ac24 vddio ad5 vddio ad8 vddio ad12 vddio ad16 vddio ad20 vddio ae26 vddio af1 vddio af25 vssc c5 vssc c10 vssc c17 vssc c22 vssc e4 vssc e12 vssc e23 vssc h4 vssc h22 vssc l5 vssc l22 vssc p26 vssc t5 vssc v4 vssc v23 vssc y5 vssc y22 vssc ab8 vssc ab12 vssc ab15 vssc ab19 vssc ac5 vssc ac22 vssio a1 vssio a25 vssio b26 vssio c4 vssio c8 vssio c12 vssio c16 vssio c20 vssio d24 vssio e2 vssio e5 vssio e9 vssio e13 vssio e17 vssio e21 vssio f22 vssio g3 vssio h24 vssio j5 vssio k22 vssio l3 vssio l11 vssio l12 vssio l13 vssio l14 vssio l15 vssio l16 vssio m11 vssio m12 vssio m13 vssio m14 vssio m15 vssio m16 vssio m24 vssio n5 vssio n11 vssio n12 vssio n13 vssio n14 vssio n15 vssio n16 vssio p11 vssio p12 vssio p13 vssio p14 vssio p15 vssio p16 vssio p22 vssio r3 vssio r11 vssio r12 vssio r13 vssio r14 vssio r15 signal ball # signal ball # signal ball #
7-18 speci?ations copyright 2002, 2003 by lsi logic corporation. all rights reserved. 7.4 mechanical drawing figure 7.5 shows the mechanical drawing for the 456-pad pbga. figure 7.5 456-pad plastic ball grid array impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code j7.
package thermal considerations 7-19 copyright 2002, 2003 by lsi logic corporation. all rights reserved. 7.5 package thermal considerations package thermal management is an important element of electronic product design. in any system environment, it is important not to exceed the maximum recommended semiconductor junction temperature. the maximum recommended junction temperature for the LSIFC929X is 115 ?c. to that end, lsi logic recommends using an appropriate heat sink for the LSIFC929X and maintaining an adequate airflow throughout the system. allowing for a maximum dynamic power consumption of 4 w, table 7.16 shows some examples of the maximum allowable junction temperature to maintain less than a 70 ?c ambient for the given air?w and heat sink conditions. table 7.16 maximum allowable ambient temperature vs. air?w air?w (m/s) jmamax (?c/w) junction temperature at 70 ?c ambient (?c) maximum allowable ambient temperature (?c) with heat sink 0 12.2 118.8 66.2 0.5 10.1 110.4 74.6 1.0 8.7 104.8 80.2 2.0 6.9 97.6 87.4 3.0 6.2 94.8 90.2 without heat sink 0 15.3 131.2 53.8 0.5 13.4 123.6 61.4 1.0 12.8 121.2 63.8 2.0 11.9 117.6 67.4 3.0 11.1 114.4 70.6
7-20 speci?ations copyright 2002, 2003 by lsi logic corporation. all rights reserved.
LSIFC929X dual channel fibre channel i/o processor technical manual a-1 copyright 2002, 2003 by lsi logic corporation. all rights reserved. appendix a register summary table a.1 and table a.2 list the register summary for the LSIFC929X. table a.1 LSIFC929X multifunction pci registers register name address read/write page vendor id 0x00 read only 6-4 device id 0x02 read only 6-4 command 0x04 read/write 6-5 status 0x06 read/write 6-7 revision id 0x08 read/write 6-9 class code 0x09 read/write 6-9 cache line size 0x0c read/write 6-10 latency timer 0x0d read/write 6-10 header type 0x0e read only 6-11 reserved 0x0f read only 6-11 i/o base address 0x10 read/write 6-12 memory[0] base address low 0x14 read/write 6-12 memory[0] base address high 0x18 read/write 6-13 memory[1] base address low 0x1c read/write 6-13 memory[1] base address high 0x20 read/write 6-14 reserved 0x24?x28 read only 6-14 subsystem vendor id 0x2c read only 6-15 subsystem id 0x2e read only 6-15
a-2 register summary copyright 2002, 2003 by lsi logic corporation. all rights reserved. expansion rom base address 0x30 read/write 6-16 capabilities pointer 0x34 read only 6-17 reserved 0x38 read only 6-18 interrupt line 0x3c read/write 6-18 interrupt pin 0x3d read only 6-18 minimum grant 0x3e read only 6-19 minimum latency 0x3f read only 6-19 power management capability id 0xxx read only 6-20 power management next pointer 0xxx read only 6-20 power management capabilities 0xxx read only 6-21 power management control/status 0xxx read/write 6-22 power management bridge support extensions 0xxx read only 6-23 power management data 0xxx read only 6-23 msi capability id 0xxx read only 6-23 msi next pointer 0xxx read only 6-24 message control 0xxx read/write 6-24 message address 0xxx read/write 6-26 message upper address 0xxx read/write 6-26 message data 0xxx read/write 6-27 pci-x capability id 0xxx read only 6-27 pci-x next pointer 0xxx read only 6-28 pci-x command 0xxx read/write 6-28 pci-x status 0xxx read/write 6-30 table a.1 LSIFC929X multifunction pci registers (cont.) register name address read/write page
a-3 copyright 2002, 2003 by lsi logic corporation. all rights reserved. table a.2 LSIFC929X host interface registers register name address read/write page system doorbell 0x00 read/write 6-34 write sequence 0x04 read/write 6-35 host diagnostic 0x08 read/write 6-36 test base address 0x0c read/write 6-38 diagnostic read/write data 0x10 read/write 6-38 diagnostic read/write address 0x14 read/write 6-39 host interrupt status 0x30 read only 6-40 host interrupt mask 0x34 read/write 6-41 request fifo 0x40 read/write 6-42 reply fifo 0x44 read/write 6-43 host index register 0x50 read/write 6-43
a-4 register summary copyright 2002, 2003 by lsi logic corporation. all rights reserved.
LSIFC929X dual channel fibre channel i/o processor technical manual b-1 copyright 2002, 2003 by lsi logic corporation. all rights reserved. appendix b reference speci?ations the LSIFC929X is compliant with the following speci?ations: table b.1 reference speci?ations speci?ation revision fibre channel physical interface (fc-pi) 11 fibre channel physical and signaling interface (fc-ph) 4.3 fibre channel arbitrated loop (fc-al-2) 7.0 fc private loop direct attach (fc-plda) 1.5 fibre channel protocol for scsi (fcp) 12 gbic 5.4 pci local bus 2.2 pci-x addendum to the pci local bus 1.0a
b-2 reference speci?ations copyright 2002, 2003 by lsi logic corporation. all rights reserved.
LSIFC929X dual channel fibre channel i/o processor technical manual c-1 copyright 2002, 2003 by lsi logic corporation. all rights reserved. appendix c glossary of terms and abbreviations 8b/10b a data encoding scheme, developed by ibm, that translates byte wide data to an encoded 10-bit format. ansi american national standards institute, the coordinating organization for voluntary standards in the united states. arbitrated loop topology (fc-al) a fc topology that provides a low cost solution to attach multiple ports in a loop without switches. ber bit error rate. bit a binary digit. the smallest unit of information a computer uses. the value of a bit (0 or 1) represents a two-way choice, such as on or off, and true or false. broadcast sending a transmission to all n_ports on a fabric. bus a collection of unbroken signal lines across which information is transmitted from one part of a computer system to another. connections to the bus are made using taps on the lines. bus mastering a high-performance way to transfer data. the host adapter controls the transfer of data directly to and from system memory without bothering the computers microprocessor. this is the fastest way for multitasking operating systems to transfer data. byte a unit of information consisting of eight bits. channel a point-to-point link, the main task of which is to transport data from one point to another.
c-2 glossary of terms and abbreviations copyright 2002, 2003 by lsi logic corporation. all rights reserved. con?uration refers to the way a computer is set up; the combined hardware components (computer, monitor, keyboard, and peripheral devices) that make up a computer system; or the software settings that allow the hardware components to communicate with each other. cpu central processing unit. the ?rain of the computer that performs the actual computations. the term microprocessor unit (mpu) is also used. crosspoint- switched topology (fc-xs) highest performance fc fabric, providing a choice of multiple path routings between pairs of f_ports. dma direct memory access. a method of moving data from a storage device directly to ram without using the resources of the cpu. dma bus master a feature that allows a peripheral to control the ?w of data to and from system memory by blocks, as opposed to pio (programmed i/o), where the processor is in control and the ?w is by byte. device driver a program that allows a microprocessor (through the operating system) to direct the operation of a peripheral device. eeprom electronically erasable programmable read only memory. a memory chip that typically stores con?uration information. eisa extended industry standard architecture. an extension of the 16-bit isa bus standard. it allows devices to perform 32-bit data transfers. exchange a term that refers to one of the fc ?uilding blocks? composed of one or more nonconcurrent sequences for a single operation. fabric fc-de?ed interconnection methodology that handles routing in fc networks. fc fibre channel. fc-ph fc physical standard, consisting of the three lower levels: fc-0, fc-1, and fc-2. fc-0 lowest level of fc-ph, covering the physical characteristics of the interface and media. fc-1 middle level of fc-ph, de?ing the 8b/10b encoding/decoding and transmission protocol.
c-3 copyright 2002, 2003 by lsi logic corporation. all rights reserved. fc-2 highest level of fc-ph, de?ing the rules for signaling protocol and describing transfer of the frame, sequence, and exchanges. fc-3 the hierarchical level in the fc standard that provides common services, such as striping de?ition. fc-4 the hierarchical level in the fc standard that speci?s the mapping of upper layer protocols (ulps) to levels below. fcc federal communications commission. fcp fibre channel protocol. fddi fiber distributed data interface. the ansi option for a metropolitan area network (man); a network based on the use of optical ?er cable to transmit data at 100 mbits/s. fibre channel service protocol (fsp) the common fc-4 level protocol for all services, transparent to the fabric type or topology. file a named collection of information stored on a disk. firmware software that is permanently stored in rom. therefore, it can be accessed during boot time. f_port ?abric port, the access point of the fabric for physically connecting the n_port. fl_port a fabric port con?ured for loop functionality. frame a linear set of transmitted bits that de?e a basic transport element. hard disk a disk made of metal and permanently sealed into a drive cartridge. a hard disk can store very large amounts of information. hal hardware abstraction layer. hippi high performance parallel interface, an 800 mbit/s interface to supercomputer networks (formerly known as high speed channel) developed by ansi. host the computer system in which a scsi host adapter is installed. it uses the scsi host adapter to transfer information to and from devices attached to the scsi bus.
c-4 glossary of terms and abbreviations copyright 2002, 2003 by lsi logic corporation. all rights reserved. host adapter a circuit board or integrated circuit that provides a scsi bus connection to the computer system. iop i/o processor. ip internet protocol. ipi intelligent peripheral interface. isa industry standard architecture. a type of computer bus used in most pcs. it allows devices to send and receive data up to 16 bits at a time. kbyte kilobyte. a measure of computer storage equal to 1024 bytes. lct logical con?uration table. link_control_ facility a termination card that handles the logical and physical control of the fc link for each mode of use. llc logical link control. local bus a way to connect peripherals directly to computer memory. it bypasses the slower isa and eisa buses. pci is a local bus standard. login server entity within the fc fabric that receives and responds to login requests. l_port an fc port which supports the arbitrated loop topology. lun logical unit number. an identi?r, zero to seven, for a logical unit. mbyte megabyte. a measure of computer storage equal to 1024 kilobytes. mfa message frame address. msi message signaled interrupt. multicast refers to delivering a single transmission to multiple destination n_ports. nic network interface card. n_port ?ode port, an fc-de?ed hardware entity at the node end of a link. nl_port a node port con?ured for loop functionality.
c-5 copyright 2002, 2003 by lsi logic corporation. all rights reserved. operating system a program that organizes the internal activities of the computer and its peripheral devices. an operating system performs basic tasks such as moving data to and from devices, and managing information in memory. it also provides the user interface. operation a term, de?ed in fc-2, that refers to one of the fc building blocks composed of one or more, possibly concurrent, exchanges. ordered set an fc term referring to four 10-bit characters (a combination of data and special characters) that provide low level link functions, such as frame demarcation and signaling between two ends of a link. it provides for initialization of the link after power-on and for some basic recovery actions. originator an fc term referring to the initiating device. parity checking a way to verify the accuracy of data transmitted over the scsi bus. one bit in the transfer makes the sum of all the 1 bits either odd or even (for odd or even parity). if the sum is not correct, an error message appears. pci peripheral component interconnect. a local bus speci?ation that allows connection of peripherals directly to computer memory. it bypasses the slower isa and eisa buses. pdb packet descriptor block. pio programmed input/output. a way the cpu can transfer data to and from memory using the computer i/o ports. pio is usually faster than dma, but requires cpu time. port the hardware entity within a node that performs data communications over the fc link. port address also port number. the address through which commands are sent to a host adapter board. this address is assigned by the pci bus. port number see port address. ram random access memory. the primary working memory of the computer in which program instructions and data are stored and are accessible to the cpu. information can be written to and read from ram. the contents of ram are lost when the computer is turned off. responder an fc term referring to the answering device.
c-6 glossary of terms and abbreviations copyright 2002, 2003 by lsi logic corporation. all rights reserved. risc core LSIFC929X chips contain a risc (reduced instruction set computer) processor, programmed through microcode scripts. rom read only memory. memory from which information can be read but not changed. the contents of rom are not erased when the computer is turned off. san storage area network. scam scsi con?uration automatically. a method that automatically allocates scsi ids using software when scam compliant scsi devices are attached. scatter/gather a device driver feature that lets the host adapter modify a transfer data pointer so that a single host adapter transfer can access many segments of memory. this minimizes interrupts and transfer overhead. scb scsi command block. scsi small computer system interface. a speci?ation for a high-performance peripheral bus and command set. the original standard is referred to as scsi-1. scsi-2 the current scsi speci?ation, which adds features to the original scsi-1 standard. scsi id a way that uniquely identi?s each scsi device on the scsi bus. each scsi bus has eight available scsi ids numbered 0? (or 0?5 for wide scsi). the host adapter usually gets id 7, giving it priority to control the bus. sequence a term referring to one of the fc building blocks, which are composed of one or more related frames for a single operation. sff small form factor. sgl scatter-gather list. snap subnetwork access protocol. synchronous data transfer one of the ways data is transferred over the scsi bus. transfers are clocked with ?ed frequency pulses. this is faster than asynchronous data transfer. synchronous data transfers are negotiated between the scsi host adapter and each scsi device.
c-7 copyright 2002, 2003 by lsi logic corporation. all rights reserved. system bios controls the low level post (power-on self test), and basic operation of the cpu and computer system. tid target id. topology the logical and/or physical arrangement of stations on a network. ulp upper layer protocol. vcci voluntary control council for interference. virtual memory space on a hard disk that can be used as if it were ram. vpd vendor product data. word a 2-byte (or 16-bit) unit of information. x3t9 a technical committee of the accredited standards committee x3, titled x3t9 i/o interfaces. it develops standards for moving data in and out of central computers.
c-8 glossary of terms and abbreviations copyright 2002, 2003 by lsi logic corporation. all rights reserved.
LSIFC929X dual channel fibre channel i/o processor technical manual ix-1 copyright 2002, 2003 by lsi logic corporation. all rights reserved. index numerics 133 mhz capable bit 6-31 133 mhz pci-x bit 6-31 4 ma bidirectional signals 7-4 64-bit address capable bit 6-24 64-bit device bit 6-31 64en/ 4-6 66 mhz capable 6-8 8 ma output signals 7-5 8b/10b decoding 2-3 8b/10b encoding 2-3 a ac timing 7-7 ack64/ 4-3 ad[1:0] 5-2 ad[10:8] 5-2 ad[63:0] 4-4 ad[7:2] 5-2 address/data bus 6-31 adsc/ 4-13 adv/ 4-13 alias to memory read block 5-4 , 5-6 , 5-7 alias to memory write block 5-4 , 5-6 alignment 5-8 arbitrated loop topology 2-8 arbitration 5-9 architecture 1-6 arm966e-s 6-36 aux_current bit 6-21 b base address register zero 5-3 ber 1-9 bios 5-2 bit error rate 1-9 block diagram 3-2 burst size selection 5-7 bus commands 5-4 bus mastering 5-9 functions 5-9 bus number 6-31 bwe[3:0]/ 4-13 bypass0/ 4-8 bypass1/ 4-8 c c_be[3:0]/ 5-2 , 5-3 , 5-4 , 5-6 , 5-7 c_be[7:0]/ 4-4 cache line size 5-7 , 5-8 , 5-9 , 6-10 cache line size alignment 5-8 cache line size register 6-10 capabilities pointer register 6-17 capability id 6-2 msi 6-23 pci-x 6-27 power management 6-20 capacitance 7-4 channel protocol 2-2 class 1 2-9 class 2 2-9 class 3 2-9 class code register 6-9 class intermix 2-10 classes of service 2-9 cls 6-10 cls alignment 5-8 command descriptor block (cdb) 2-6 command register 6-5 configuration read command 5-2 , 5-4 , 5-6 , 5-7 , 6-7 write command 5-2 , 5-4 , 5-6 , 5-7 , 6-7 configuration space 5-2 , 6-1 , 6-2 ad[1:0] 5-2 ad[10:8] 5-2 ad[7:2] 5-2 c_be[3:0]/ 5-2 , 5-3 , 5-4 context manager 1-8 controller link 1-8 memory 1-7 crc 2-4 cyclic redundancy check (crc) 2-4 d d0 6-22 d1 bit 6-21 d2 bit 6-21 d3 6-22 dac 5-1 , 5-4 , 5-8 data parity error reported 6-8 data flows 3-2 data frames 2-4 data parity error recovery enable bit 6-29
ix-2 index copyright 2002, 2003 by lsi logic corporation. all rights reserved. data sequence 2-6 data_scale bit 6-22 data_select bit 6-22 decoding 8b/10b 2-3 designed maximum cumulative read size bit 6-30 designed maximum memory read byte count bit 6-30 designed maximum outstanding split transactions bit 6-30 destination identifier (d_id) 2-8 detected parity error (from slave) bit 6-7 device complexity bit 6-31 device id register 6-4 device number bit 6-32 device specific initialization bit 6-21 devsel/ 4-5 devsel/ timing bit 6-7 diagnostic memory 6-32 diagnostic memory enable bit 6-37 diagnostic read/write address register 6-39 diagnostic read/write data register 6-38 diagnostic read/write enable bit 6-37 diagnostic write enable bit 6-36 disarm bit 6-37 dma 5-9 doorbell status bit 6-40 system interrupt bit 6-40 doorbell interrupt mask bit 6-42 dual address cycle (dac) 1-7 dual address cycles command 5-1 , 5-4 , 5-8 e enable bus mastering bit 6-6 diagnostic memory bit 6-37 diagnostic write bit 6-36 i/o space bit 6-6 memory space bit 6-6 msi bit 6-25 parity error response bit 6-6 write and invalidate bit 6-6 encode/decode 2-3 end-of-frame (eof) 2-4 enum/ 4-6 exchanges transfer 2-3 expansion rom base address register 6-16 expansion rom enable bit 6-16 f fabric topology 2-8 fault0/ 4-7 fault1/ 4-8 fc data structure 2-5 data traffic 3-1 devices 2-7 exchange 2-5 fibre channel 2-1 frames 2-5 interface 2-2 layer 2-3 link 1-8 n_ports 2-3 sequence 2-5 structure 2-2 word 2-5 fcp 2-5 exchange 2-6 fibre channel protocol 1-1 fibre channel (fc) 2-1 fibre channel protocol (fcp) 1-1 fifo reply 6-43 request 6-42 flash rom bad signature bit 6-36 flash rom read timing 7-9 flash rom write timing 7-10 flashcs/ 4-12 frame data 2-4 end of 2-4 link control 2-4 payload 2-6 start of 2-4 transfer 2-3 frame/ 4-4 function number bit 6-32 functional block diagram 1-7 functional signal grouping 4-2 g gigablaze transceiver 3-2 gnt/ 4-3 , 5-9 gpio[2](blueled/) 4-6 gpio[3:0] 4-14 grant 5-9 h header type register 6-11 host diagnostic register 6-36 host doorbell value 6-34 host interrupt mask register 6-41 host interrupt status register 6-40 hotswapen/ 4-6 i i/o base address register 5-3 , 6-12 key 6-35 read command 5-4 , 5-5 , 5-7 space 5-3 , 6-1 , 6-32 write command 5-4 , 5-5 , 5-7 iddtn 4-15 idsel 4-4 , 5-2 implementation 1-5 , 3-9 initiator command sequence 2-6 input signals 7-4 inta/ 4-5 , 6-37 intb/ 4-6 integrated transceiver 1-8 integration 2-3 interface fc 2-2 media 2-3 system 1-7 , 1-8 upper level protocol (ulp) 2-2
index ix-3 copyright 2002, 2003 by lsi logic corporation. all rights reserved. interface timing ssram read/write/read 7-8 intermix class 2-10 internet protocol (ip) 2-2 interrupt acknowledge command 5-4 , 5-5 , 5-7 doorbell mask bit 6-42 line register 6-18 pin register 6-18 reply bit 6-40 reply mask bit 6-42 request routing mode bits 6-41 signal routing 6-41 system doorbell bit 6-40 ttl bit 6-37 iop doorbell status bit 6-40 irdy/ 4-5 k key i/o 6-35 l lan message interface 3-6 lan protocol stack 3-7 latency timer register 6-10 led[4:0]/ 4-14 link control frames 2-4 link controller 1-8 lipreset/ 4-7 m ma[21:0] 4-11 maximum ambient temperature 7-19 maximum latency register 6-19 maximum memory read byte count bits 6-29 maximum outstanding split transactions bits 6-28 maximum stress ratings 7-3 mclk 4-13 md[31:0] 4-10 media interface 2-3 memory alias to read block 5-6 , 5-7 alias to write block 5-4 , 5-6 read block command 5-4 , 5-6 , 5-7 , 5-8 read command 5-4 , 5-5 , 5-7 , 5-8 , 5-9 read dword command 5-4 , 5-5 , 5-7 read line command 5-4 , 5-8 , 5-9 read multiple command 5-4 , 5-7 , 5-9 space 5-3 , 6-1 write and invalidate command 5-4 , 5-8 , 5-9 write block command 5-4 , 5-6 , 5-9 write command 5-4 , 5-6 , 5-8 , 5-9 memory [0] high register 6-13 memory [0] low register 6-12 memory [1] high register 6-14 memory [1] low register 6-13 memory controller 1-7 memory shared 6-44 memory space [0] 5-3 , 6-1 , 6-32 memory space [1] 5-3 , 6-1 memory space[1] 6-32 message address register 6-26 message control register 6-24 message data register 6-27 message flow 3-5 message interface 3-3 message queueing models 3-4 message transport 1-7 message upper address register 6-26 minimum grant register 6-19 mode[7:0] 4-14 modef0[2:0] 4-9 modef1[2:0] 4-9 moe[1:0] 4-12 mp[3:0] 4-10 msi capability id register 6-23 enable bit 6-25 next pointer register 6-24 multifunction pci 5-2 multiple cache line transfers 5-9 multiple message bits 6-25 mwe[1:0]/ 4-12 n new capabilities 6-8 o odis0 4-8 odis1 4-8 operating conditions 7-3 overview 1-1 1-3 p packaging 7-18 , 7-19 par 4-5 par64 4-5 parity error 6-8 payload 2-4 , 2-6 pci 66 mhz capable 6-8 address/data bus 6-31 addressing 5-2 alias to memory read block command 5-6 , 5-7 alias to memory write block command 5-6 arbitration 5-9 bus commands 5-3 , 5-4 bus commands and encoding types 5-4 cache line size register 5-8 cache mode 5-9 command 5-4 configuration read 5-2 configuration write 5-2 dual address cycles 5-1 memory read block 5-6 memory write 5-6 configuration read command 5-4 , 5-6 , 5-7 , 6-7 configuration space 5-2 , 6-1 , 6-2 ad[1:0] 5-2 ad[10:8] 5-2 ad[7:2] 5-2 address map 6-3 c_be[3:0]/ 5-2 , 5-3 , 5-4 configuration write command 5-4 , 5-6 , 5-7 , 6-7 dac 5-1 , 5-4 , 5-8
ix-4 index copyright 2002, 2003 by lsi logic corporation. all rights reserved. dual address cycles command 5-4 , 5-8 functional description 5-1 i/o read command 5-4 , 5-5 , 5-7 i/o space 5-2 , 5-3 , 6-1 , 6-32 i/o space address map 6-33 i/o space and memory space [0] 6-32 i/o write command 5-4 , 5-5 , 5-7 interrupt acknowledge command 5-4 , 5-5 , 5-7 memory [0] address map 6-33 memory [1] address map 6-34 memory read block command 5-7 , 5-8 memory read command 5-4 , 5-5 , 5-7 , 5-8 , 5-9 memory read dword command 5-5 , 5-7 memory read line command 5-4 , 5-8 , 5-9 memory read multiple command 5-4 , 5-7 , 5-9 memory space 5-2 , 5-3 , 6-1 memory space [0] 5-3 , 6-1 memory space [1] 5-3 , 6-1 memory write and invalidate command 5-4 , 5-8 , 5-9 memory write block command 5-6 , 5-9 memory write command 5-4 , 5-8 , 5-9 multifunction 5-2 new capabilities 6-8 reset 6-37 special cycle command 5-4 , 5-5 , 6-7 split completion command 5-7 system address space 6-1 pci bidirectional signals 7-6 pci input signals 7-5 pci output signals 7-6 pciclk 4-3 pci-x 5-1 133 mhz capable bit 6-31 64-bit device bit 6-31 alias to memory read block command 5-4 alias to memory write block command 5-4 bus commands 5-4 bus number 6-31 capability id register 6-27 capability register 6-27 command 5-4 command register 6-28 data parity error recovery enable bit 6-29 designed maximum cumulative read size bit 6-30 designed maximum memory read byte count bit 6-30 designed maximum outstanding split transactions bit 6-30 device complexity bit 6-31 device number bit 6-32 function number bit 6-32 maximum memory read byte count bits 6-29 maximum outstanding split transactions bits 6-28 memory read block command 5-4 memory read dword command 5-4 memory write block command 5-4 next pointer register 6-28 received split completion error message bit 6-30 split completion command 5-4 split completion discarded bit 6-31 status register 6-30 unexpected split completion bit 6-31 perr/ 4-5 pme enable bit 6-22 status bit 6-22 support bits 6-21 pme clock bit 6-21 point-to-point topology 2-8 por 6-37 ports 2-7 power management aux_current bit 6-21 bridge support extensions register 6-23 capabilities register 6-21 capability id register 6-20 control/status register 6-22 d0 6-22 d1 bit 6-21 d2 bit 6-21 d3 6-22 data register 6-23 data_scale bit 6-22 data_select bit 6-22 device specific initialization bit 6-21 next pointer register 6-20 pme clock bit 6-21 pme enable bit 6-22 pme status bit 6-22 power state bit 6-22 support bits 6-21 version bit 6-21 power on reset 6-37 power state bit 6-22 proc_drvls 4-15 processor arm risc 1-6 , 1-7 , 1-8 i/o 1-7 protocol channel 2-2 fibre channel (fcp) 1-1 , 2-5 internet 2-2 signaling 2-3 transmission 2-3 upper level 2-2 protocols upper layer 2-3 r ramcs/ 4-13 received master abort (from master) bit 6-7 target abort (from master) bit 6-7 received split completion error message bit 6-30 receiver 1-8 refclk 4-9 reference specifications b-1 register cache line size 6-10 capabilities pointer 6-17 class code 6-9 command 6-5 device id 6-4 diagnostic read/write address 6-39 diagnostic read/write data 6-38 expansion rom base address 6-16 header type 6-11 host diagnostic 6-36 host interrupt mask 6-41 host interrupt status 6-40 i/o base address 6-12 interrupt line 6-18 interrupt pin 6-18
index ix-5 copyright 2002, 2003 by lsi logic corporation. all rights reserved. latency timer 6-10 map pci i/o space 6-33 maximum latency 6-19 memory [0] high 6-13 memory [0] low 6-12 memory [1] high 6-14 memory [1] low 6-13 message address 6-26 message control 6-24 message data 6-27 message upper address 6-26 minimum grant 6-19 msi capability id 6-23 msi next pointer 6-24 pci memory [0] address map 6-33 pci memory [1] address map 6-34 pci-x capability 6-27 pci-x capability id 6-27 pci-x command 6-28 pci-x next pointer 6-28 pci-x status 6-30 power management bridge support extensions 6-23 power management capabilities 6-21 power management capability id 6-20 power management control/status 6-22 power management data 6-23 power management next pointer 6-20 reply fifo 6-43 request fifo 6-42 revision id 6-9 status 6-7 subsystem id 6-15 subsystem vendor id 6-15 system doorbell 6-34 test base address 6-38 vendor id 6-4 write sequence 6-35 register map a-1 , a-3 pci configuration space 6-3 reply fifo register 6-43 reply interrupt bit 6-40 reply interrupt mask bit 6-42 reply message 3-3 reply message frames 5-9 req/ 4-3 , 5-9 req64/ 4-3 request fifo register 6-42 request message 3-3 request message frames 5-9 request status 1-9 reset adapter bit 6-37 reset history bit 6-37 response sequence 2-6 revision id register 6-9 rom expansion enable bit 6-16 rst/ 4-3 rtrim 4-7 rx0neg 4-7 rx0pos 4-7 rx1neg 4-7 rx1pos 4-7 rxlos0 4-8 rxlos1 4-9 s schmitt input signals 7-4 scl 4-14 scsi bus mastering functions 5-9 functions 5-9 scsi message interface 3-6 sda 4-14 sequences transfer 2-3 serr/ 4-5 , 6-29 serr/ enable bit 6-5 shared memory 6-44 signaled system error bit 6-7 signaling protocol 2-3 special cycle command 5-4 , 5-5 , 6-7 split completion command 5-4 , 5-7 split completion discarded bit 6-31 ssram memory 3-9 start-of-frame (sof) 2-4 status iop doorbell bit 6-40 status register 6-7 stop/ 4-5 subsystem id register 6-15 subsystem vendor id register 6-15 support components 3-8 flash rom 3-10 serial eeprom 3-10 ssram memory 3-9 switch/ 4-6 system address space 6-1 system bios 5-2 system doorbell interrupt bit 6-40 system doorbell register 6-34 system interface 1-7 , 1-8 , 5-9 bus mastering function 5-9 t target message class 3-8 target operation 1-9 target response 2-6 tck 4-15 tdi 4-15 tdo 4-15 test base address register 6-38 testreset/ 6-37 timing diagram flash rom read 7-9 flash rom write 7-10 ssram read/write/read 7-8 tms_chip 4-15 tms_ice 4-15 topology arbitrated loop 2-7 fabric 2-7 point-to-point 2-7 transceiver 1-8 , 3-2 transfer exchanges 2-3 frames 2-3 sequences 2-3 transmission protocol 2-3 transmitter 1-8 trdy/ 4-5 trst 4-15
ix-6 index copyright 2002, 2003 by lsi logic corporation. all rights reserved. ttl interrupt bit 6-37 tx0neg 4-7 tx0pos 4-7 tx1neg 4-7 tx1pos 4-7 u unexpected split completion bit 6-31 upper layer protocols (ulps) 2-3 v vendor id register 6-4 version bit 6-21 w write and invalidate enable bit 6-6 write i/o key 6-35 write sequence register 6-35 z zz 4-13
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